ArF Immersion Research Articles

Theoretical study of fabrication of line-and-space patterns with 7 nm quarter-pitch using electron beam lithography with chemically amplified resist processes: II. Stochastic effects

Electron beam (EB) lithography is a core technology for nanofabrication. Owing to the increasing demand for high-resolution semiconductor lithography, the requirements for the resist processes of EB lithography for the photomasks used in ArF immersion and extreme ultraviolet lithographies and the mold fabrication of nanoimprints have also become stricter. In this study, the feasibility of single nano patterning by EB lithography with a chemically amplified resist process was investigated from the viewpoint of stochastic effects. The latent images of line-and-space patterns with a 7 nm quarter-pitch (7 nm space width and 21 nm line width) were calculated using a Monte Carlo method on the basis of the sensitization and reaction mechanisms of chemically amplified EB resists. Compared with the line-and-space pattern with a 7 nm half-pitch, line edge roughness (LER) and the stochastic pinching generation are considered to be significantly improved by increasing the pitch. It was found that the suppression of the stochastic generation of bridges is the critical issue in 7 nm quarter-pitch fabrication.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Optimum waveguide-core size for reducing device property distribution of Si-wire waveguide devices

We investigated the waveguide-core size distribution of ring resonators fabricated on a 300 mm silicon-on-insulator (SOI) wafer using a CMOS-compatible process featuring ArF immersion lithography. These ring resonators were constructed in a Si-wire waveguide with a standard core size of 400 nm width and 220 nm height. The group refractive indices of the waveguide were derived from the transmission spectra of the ring resonators. From the deviation of these group refractive indices, the waveguide-core width distribution was estimated to be 5 nm, and the waveguide-core height distribution was estimated to be 1 nm. Moreover, the device property distribution of various Si-wire waveguide depended on the estimated fabrication error was calculated. The waveguide core with the smallest device property distribution had a 540 nm width and a 160 nm height, and this waveguide has a device property distribution of 2/3 value compared with the standard core size.

Directed self-assembly lithography for half-pitch sub-15 nm pattern fabrication process

ABSTRACTThis paper introduces a fabrication method to achieve sub-15 nm line-and-space (L/S) patterns by combining grapho- and chemo-epitaxy using poly(styrene-block-methyl methacrylate) copolymer (PS-b-PMMA). The fabrication method is simple, since it eliminates photoresist stripping and also does not require any special materials to form pinning patterns. In this process, the ridges formed on spin-on-glass (SOG) surface work as physical guides and the photoresists on them are utilized as a pinning layer. Fine PS-b-PMMA L/S patterns were obtained in sufficient critical dimension (CD) range of the guide patterns that corresponded to the 15% dose margin using ArF immersion lithography. 3-dimensional grid defects were found to be the origin of the short defects. The half-pitch (hp) 15 nm L/S patterns were transferred successfully to SOG/spin-on-carbon (SOC) stacked substrate.We also describe fabrication of sub-10 nm L/S patterns using a high-chi block copolymer (BCP).

Novel Clean Concept of Advanced Patterning Film (Amorphous Carbon) for Beyond 2xnm Generation Self-Aligned Double-Patterning (SADP) Process

Advanced Patterning Film (APF, Amorphous Carbon) is newly developed hard mask material by APPLY MATERIALS, Inc. for fine pattern definition, especially used in ArF immersion process. However, amorphous carbon is one candidate of core materials of self align double pattering (SADP) process, usually suggested not to use wet clean process after patter definition due to moisture absorption of APF. We successfully demonstrate better amorphous carbon surface clean performance without any film damaged and line edge roughness (LER) improve 18.2% CD variation, 1.1nm in space even-odd bias beyond 28nm generation. APF of APPLY MATERIALS, Inc. is chemical vapor deposition (CVD) amorphous carbon (a-C) which precursors are normally acetylene (C2H2) and propane (C3H6). Traditional post clean SPM chemical consists of sulfuric acid (H2SO4) and hydro peroxide (H2O2). Hydro peroxide will oxidize amorphous carbon into CO or CO2and result in pattern damaged. We surveyed some post clean candidates in semiconductor fabrication common used, as table 1 shows. Only APM and DHF showed miner or no etching rate to amorphous carbon film. APM is first chosen chemical for amorphous carbon core post etching clean. In Figure 1-a, 3nm/side etching polymer is found on a-C sidewall, and Figure 1-b shows that dry etching polymer are totally removed after APM 10 minutes treatment. However, in SADP process, core material should be with higher removal rate than spacer material, which is usually selected by high temperature deposition film to achieve the high selectivity to core material in core removal process.As Figure 2 shows, amorphous carbon with C2H2precursor is porous structure. 10 minutes APM process will induce moisture absorption by porous amorphous carbon film and line twist in following high temperature spacer material deposition, 450C atomic layer deposition silicon nitride, shows as Figure 3-a. Figure 3-b shows worse even-odd spacer bias after SADP spacer defined. Shorter clean process time and high clean efficiency become the keys of a-C core post clean step. Two chemicals A and B, A is higher fluorine concentration contained and B is lower fluorine concentration contained, a-C core post clean efficiency were investigated and both process times are confined within 90 seconds, including rinse and drying steps. Figure 4-a., 4-b. and 4-c show chemical A has better polymer removal capability than chemical B. Line edge roughness (LER) is reduced from 3.03nm to 2.48nm, 18.2% improvement, shows as Figure 5. In Figure 6 good LER and even-odd space performance of SADP gate definition after adopting chemical A for a-C post etching clean. Long time clean process will result in water absorption of amorphous carbon film due to its porous structure, and will cause worse line edge roughness (LER) in the following high temperature spacer material deposition process. Shorten clean process time to avoid water absorption and improve clean efficiency are the major criteria to achieve successful amorphous carbon clean. Novel a-C clean method by raising F concentration to achieve higher clean efficiency and successfully improve LER 18.2% after core etching and post clean in positive tone SADP process beyond 2xnm generation.

Novel Clean Concept of Advanced Patterning Film (Amorphous Carbon) for Beyond 2xnm Generation Self-Aligned Double-Patterning (SADP) Process

Advanced Patterning Film (APF, Amorphous Carbon) is newly developed hard mask material by APPLIED MATERIALS, Inc. for fine pattern definition, especially used in ArF immersion process. Amorphous carbon is one candidate of core materials of Self-Aligned Double-Pattering (SADP) process, but it is usually suggested not to use wet clean process after pattern definition due to moisture absorption of APF. We successfully demonstrate better amorphous carbon surface clean performance without any film damaged. Line edge roughness (LER) is improved from 3.03nm to 2.48nm (18.2%) and without pattern even-odd space issue beyond 2xnm generation.

The Critical Role of the Plasma-Based Post Litho Treatment

Since CMOS technology moved to 28nm node and beyond, ArF immersion lithography process already reached its limitation from the point of view of line width roughness (LWR) and photo resist (PR) profile control. The majority of this work focused on the modification of PR surface morphology at poly-gate LWR, poly-gate line-cut, contact etch and metal hard-mask open process by means of plasma-based post litho treatment (PPLT). Results indicate the 15% LWR improvement has been achieved with the optimized PPLT for poly-si gate, PPLT is also a must-have step at poly-gate line-cut process to alleviate the impact of poor PR sidewall roughness and marginal OPC window, and ensure the on-target head-to-head space without any bridge issue. OUL step is the key step to deliver the much smaller head-to-head space. The capability of different etching gases at optical under-layer (OUL) are compared in terms of head-to-head space and bridge defect. Besides, we also demonstrated PPLT is effective to greatly improve the PR footing profile/scumming induced DVC (Dark voltage contrast) and high Rc issue at contact etch. Briefly, PPLT can remarkably extend the lithography process window and demonstrate the robust overall fabrication performance.

Compact PIN-Diode-Based Silicon Modulator Using Side-Wall-Grating Waveguide

We developed PIN-diode-based silicon Mach-Zehnder modulators, which have side-wall-gratings in the phase-shifter sections. Such passive waveguides with gratings were fabricated using ArF immersion lithography, which showed a small scattering loss of 0.4 dB/mm. We extensively investigated the forward-biased operation of the modulators by using equivalent circuit analysis and the measurement of the fabricated devices. We argue carrier recombination time only plays a minor role for the overall performance of the modulator. Dependences of the modulation efficiency on other various critical parameters are discussed. In particular, if we use relatively short phase shifter, the forward-biased operation provides smaller VπL than reversed one even at high frequency of 20 GHz, at the expense of the narrow bandwidth. Our approach enables high-speed operation up to 50 Gb/s, by using phase shifter as short as 250 μm and preemphasis signals. For 12.5-Gb/s operation, the modulator cell size was only 300 μm × 50 μm, which was suitable for the applications of high-density optical interconnects.

Si wire array waveguide grating with stray light reduction scheme fabricated by ArF excimer immersion lithography

A Si wire arrayed waveguide grating designed to reduce the noise and transmission peak width and avoid systematic phase error generated at the curved waveguides is reported. A slab waveguide structure to remove stray light is used. 200 GHz spacing 16 channel devices were fabricated by ArF immersion. An improved crosstalk of −23 dB was obtained.

(Invited) Negative Tone Development Process and Resist Materials with ArF Immersion Exposure Process

Negative tone development (NTD) process was proposed as a good candidate to obtain good quality in resist pattern for trench and contact hole (C/H) pattern with ArF immersion resist process. Advantages of NTD compared to positive tone development (PTD) process are discussed in detail. High volume manufacturing capabilities, mainly in the performances of CD uniformity and defectivity, are discussed. The challenges in resist material are addressed, and the material design strategies and new resist materials are introduced.

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.

Si wire array waveguide grating with parallel star coupler configuration fabricated by ArF excimer immersion lithography

An Si wire array waveguide grating wavelength demultiplexer fabricated using immersion ArF lithography is reported. The tilt directions of the input and output star couplers are aligned in the same direction to avoid phase error generated at the curved waveguides. A 16 channel device with 200 GHz wavelength spacing was fabricated.

Material Development for ArF Immersion Extension towards Sub-20nm Node

Today ArF immersion processes are widely applied for advanced device manufacturing. ArF immersion lithography enables 4x nm half-pitch (hp) lithography. The use of double patterning extends immersion to 2x nm hp lithography. New materials for such 193nm lithography extensions are widely needed, especially for post-193nm immersion lithography technology. In this paper, we report a slimming material that makes line patterns smaller and it succeeds in forming 20nm lines.In another study, we examined a new hydrophilic lactone to improve line width roughness (LWR) and defectivity. First, we studied the lactone reactivity with developer and its behavior during development. Then we verified its line width LWR performance and defectivity. When the hydrophilic new lactone is used in a photoresist, an improvement in LWR and defectivity photoresist was observed. This is very useful progress, especially in combination with processes such as multiple patterning to extend ArF immersion to sub-20nm hp dimensions.

Functional Properties of Novel Metallic Hard Masks

Hard masks play an important role in pattern transfer to the desired substrate in the semiconductor lithography processes. Organic and inorganic type hard masks are used. While most organic hard masks such as carbon and siloxane type are solution spin coated, inorganic type hard masks such as SiON and SiN are either chemical vapor deposited (CVD) or atomic layer deposited (ALD). Future generation of lithography processes require hard masks with higher resistance to fluorinated plasma and materials that can be easily wet stripped after pattern transfer process to prevent dry etch damage to the substrate underneath.The present paper describes formation and functional properties of novel metal oxide hard masks by simple solution spin coating process. These novel metal oxide hard masks offer good etch selectivity and can easily be partially or fully wet strippable using commonly used chemicals in the FABs. The spin coatable composition has good long-term shelf life and pot life stability based on solution LPC analysis and wafer defect studies. The hard mask material absorbs DUV wavelengths and can be used as a spin-on inorganic or hybrid antireflective coating to control substrate reflectivity under DUV exposure of photoresist. At the same time they are transparent at 500-700nm for alignment mark identification and can be spin coatable up to 450nm thickness with good film quality. Some of these metal-containing materials can be used as an underlayer in EUV lithography to significantly enhance sensitivity of the photoresist. Specific metal hard masks are also developed for via or trench filling applications in IRT processes. The materials have shown good coating and lithography performance with a film thicknesses as low as 10 nm under ArF dry or immersion conditions.

ITRS lithography roadmap: status and challenges

Abstract Recent ITRS lithography roadmaps show a big technology decision approaching the semiconductor industry about how to do leading edge lithography. The need is rapidly approaching for the industry to select an option for the 22-nm half pitch, but no decision has been made yet. The main options for the 22-nm half pitch are extreme ultraviolet (EUV), ArF immersion lithography with multiple patterning, and maskless lithography. For the 16-nm half pitch, directed self-assembly (DSA) is also an option. The EUV has the most industry investment and is the closest to current lithography in the way it works but still faces challenges in tool productivity and defect-free masks. The nanoimprint needs to overcome the defect, contamination, and overlay challenges before it can be applied to the semiconductor production. Maskless lithography may be used first for prototyping and small volume products where mask costs per chip produced would be very high. Double patterning could be extended to multiple pattering, but would give tremendous process complexity and exponentially rising mask costs due to the many exposures needed per level. The DSA, which only recently has emerged from the research stage, has the potential for very high resolution but represents a huge change in how critical dimensions are formed and controlled.

Advances in EUV light sources

Abstract Extreme ultraviolet (EUV) lithography has emerged as the preferred choice for high-volume manufacturing, now that immersion ArF reaches its limits. Light source power is a key driver to achieve the throughput required for successful adoption of extreme ultraviolet lithography (EUVL). Cymer has developed a laser-produced plasma source based on a high-power CO2 drive laser exciting tin targets to emit 13.5 nm light. Five sources are currently installed at chipmaker fabs and are being used for process development. The power output of the fielded source configuration is currently 20 W, lower than required for manufacturing introduction. The technology for scaling up power is under development, focusing on increasing the conversion efficiency and collection efficiency of the source. Increasing drive laser power to 17 kW has allowed the demonstration of EUV power of nearly 50 W, with paths identified for further scaling to 100 W. An additional focus on product reliability has driven the availability up to 70%, primarily through extending the collector mirror lifetime.

DOF and Coherence Optimization in Sub-32 nm Contact Lithography

As lithography process steps into deep low k1 factor (~0.3 or smaller) generation, imaging quality and lithography process window (PW) are highly sensitive to the illumination pupil. Maintaining the depth of focus (DOF) becomes more challenging for sub-32 nm tech node micro-lithographic process especially for contact patterns, and carefully selection of accurate illumination setting is significant during the course of process development. Although Source Mask Optimization (SMO) has become one of the most important techniques available for extending ArF immersion lithography, for logic and foundry patterns, source optimization only is still an effective method to extend lithographic capability and maximize depth of focus. In this paper, we present our study on the determination of the optimized illumination mode for 28 nm contact lithography through both photolithographic simulation and experiments with different imaging coherence settings. This simulation and experimental study show that even a previously believed "tiny" sigma change, such as, 0.01 can lead to a significant effect on depth of focus, which can be as much as 30%. This indicates that photolithographic process optimization and development have entered an era where intensive simulation and parameter mapping becomes inevitable in order to achieve success. Also, the heavy dependence of an acceptable process on the illumination has put a more stringent requirement on the scanner's control on the illumination pupil's accuracy and stability.

Double Patterning Using Multilayer Hard Mask Process with Perhydropolysilazane

A new technology called the double patterning (DP) process with ArF immersion lithography is one of the candidate fabrication technologies for 32-nm-node devices. Over the past few years, many studies have been conducted on techniques of the DP process. Among these technologies, the double Si hard mask (HM) process is thought to be the most applicable technology from the viewpoint of high technical applicability to 32-nm-node device fabrication. However, this process has a disadvantage in terms of cost performance compared with other DP technologies since these HMs are formed by the chemical vacuum deposition (CVD) method. In this study, we examined the DP process using a dual spin-on Si-containing layer without using the CVD method to improve process cost and process applicability. Perhydropolysilazane (PSZ) was used as one of the middle layers (MLs). PSZ changes to SiO2 through reaction with water by the catalytic action of amine in the baking step. Using PSZ and Si-BARC as MLs, we succeeded in fabricating a fine pattern by this novel DP technique. In this paper, the issues and countermeasures of the double HM technique using spin-on Si-containing layers will be reported.

Potential applications of negative tone development in advanced lithography

Advanced lithography requires resolution enhancement techniques (customized illumination mode, litho friendly design), and alternative process flow schemes (double exposure, double patterning) in order to meet the requirements of the ITRS technology roadmap and to extend the applications of a full-field scanner with a 1.35 numerical aperture (NA) that represents the physical limit of water-based immersion ArF lithography.Today, one of the most interesting alternative processes uses the patterning inversion through a negative tone development (NTD) process step. Traditionally, the patterning (contacts or trenches) is done by using a dark field mask in combination with positive tone resist and positive tone development (PTD). By using a solvent-based developer (NTD) and a bright field mask, the same features can be transferred into a positive resist with the benefit of better image contrast and, consequently, better line width roughness (LWR) and resolution.In this work we have explored the potential applications of NTD for trenches and contact holes for the 45nm technology node requirements and beyond. The NTD process is a promising option considering the impact on process window, LWR, CD uniformity and defectivity. The experimental result of this alternative approach to print critical dark field levels in an advanced lithography boundary has been explored.

Material Development for ArF Immersion Resist Extension

ArF immersion process is being widely applied for advanced device manufacturing. ArF immersion lithography can cover 4x nm hp lithography. In addition, double patterning process allows extendibility towards 2x nm hp lithography. From the point of view of photoresist, it is utterly important for materials to bring out the maximum performance of ArF immersion process. In this study, we focused on photoresist development and substrate optimization, demonstrating good lithographic performance of sub-40nm hp resolution with well controlled line width roughness (LWR).First of all, we studied photo acid generator (PAG) behavior focusing on shortening acid diffusion length during Post Exposure Bake (PEB). Secondly, high dissolution contrast polymers in which dissolution properties are changed by acid catalyzed reaction through exposure and PEB are being studied. Thirdly, reflectivity control from substrate through optimization of light intensity over resist film thickness has been carried out. In this report, we have achieved 36.5nm line and space (LS) resolution with LWR of less than 10% of patterned critical dimension (CD). This achievement is very useful especially when utilized in combination with process tricks such as multiple patterning for extending existing ArF immersion lithography towards sub-20nm hp lithography.