ArF Immersion Research Articles

Electrical evaluation of copper damascene interconnects based on nanoimprint lithography compared with ArF immersion lithography for back-end-of-line process

Nanoimprint lithography (NIL) is promising for the processing of dual damascene structures fabricated in back-end-of-line layers, and initial development began with a simple single-level process to evaluate NIL’s suitability. In this work, a test element group (TEG) pattern with a 70 nm half-pitch was selected, and copper (Cu) filling and chemical-mechanical polishing were performed after NIL pattern transfer. The results were compared with those obtained from the same TEG layout and processes but using ArF immersion lithography instead of NIL. Those obtained by NIL showed high pattern fidelity for all the designed layouts, whereas the resist patterns varied from the designed shape for ArF immersion lithography. The line resistances of Cu interconnects patterned by NIL showed good cumulative distributions at line widths ranging from 60 nm to 78 nm in 2 nm increments, without line breaks or space narrowing of SiO2. NIL showed potential for interconnect patterning with high-precision line width control.

Physical model-based ArF photoresist formulation development

Since the logic 28 nm technology and beyond, ArF immersion lithography has been widely used in manufacturing. To fully utilize the potential of the lithographic resolution, process simulation has been used since the lithography process setup step. The accuracy of the model prediction can be a key factor in the process stability, defectivity, and yield of the final product. To get better model prediction, it is very important to develop a process model with as many parameters as possible with physical meanings. Since the analysis of exposure data with a physical model can provide insights into the process and the photoresist material, it may greatly accelerate the photoresist formulation development or improvement process. From another aspect, as the function of the photoresist is to record the aerial image information on wafer, theoretically, the photoresist image should not deviate much from the aerial image or it will inevitably reduce the information content of the aerial image, i.e., through various kinds of averaging, mixing, etc. Since the emergence of Optical Proximity Correction (OPC), the time that takes to finalize a photolithography process has been significantly lengthened and made more complicated. To make the OPC model more reliable and less dependent on patches, a more physical OPC model is necessary. Therefore, it is clear that if we can develop a photoresist formulation to realize a more physical photoresist image, or a photoresist image closer to the aerial image, we can greatly improve the photolithography process performance and the time consumed for the process setup including OPC. In this paper, we focus on several physical model parameters for photoresist, especially the effective photoacid diffusion length and photo decomposable base parameters. We will show that these two parameters can provide a good description of photoresist imaging behavior, and the resist formulation can be improved to match the physical model prediction with more accuracy.

Surface property control for 193 nm immersion resist by addition of Si compound

In ArF immersion lithography, the presence of immersion liquid between the resist surface and the lens causes problems, such as the leaching of the photoacid generator into the liquid and the presence of residual liquid on the resist surface, which can result in watermarks and other defects. One method to address such issues is adding an F-based compound with low dry-etch resistance to the resist. In the present study, we developed a novel resist for ArF immersion exposure that replaces the F compound with an Si (dimethylpolysiloxane)-based additive to enhance dry-etch resistance. We experimentally evaluated contact angles with respect to water and developer solution, depth concentration of the additives (segregation), agent dissolution (leaching), dry-etch resistance, and spectral transmittance of the comparative resists. Simulation studies were performed to evaluate pattern profiles. The developed resist with the Si-based additive showed improved properties compared with that with the F-based additive.

A Study on the Resolution and Depth of Focus of ArF Immersion Photolithography.

In this study, the resolution and depth of focus (DOF) of the ArF immersion scanner are measured experimentally according to numerical aperture (NA). Based on the experiment, the theoretical trade-off relationship between the resolution and depth of focus can be confirmed and k1 and k2 are extracted to be about 0.288 and 0.745, respectively. Another observation for a problem in small critical dimension realization is the increase in line width roughness (LWR) according to mask open area ratio. To mitigate the trade-off problem and critical dimension variation, the photoresist thickness effect on depth of focus is analyzed. Generally, the photoresist thickness is chosen considering depth of focus, which is decided by NA. In practice, the depth of focus is found to be influenced by the photoresist thickness, which can be caused by the intensity change of the reflected ArF light. This means that photoresist thickness can be optimized under a fixed NA in ArF immersion photolithography technology according to the critical dimension and pattern density of the target layer.

300 mm Large Area Wire Grid Polarizers with 50 nm Half-Pitch by ArF Immersion Lithography

The large area wire grid polarizers (LA-WGPs) with 50 nm half-pitch were fabricated using ArF immersion lithography overcoming the limit of the shot field size. To realize the 50 nm line and space patterns on a 300 mm wafer, a zero-distance stitching process that connects the shot fields is suggested. To compensate for mutual interference between the shot fields which is called the local flare effect (LFE), the shot field arrangement is changed with optical proximity correction (OPC). Using a master wafer produced by the suggested method, 300 mm large-area WGPs were fabricated by the nano-imprint process. The WGPs have more than 80% transmittance in the visible light region, and the possibility of performance improvement can be confirmed depending on the number and method of the etch process.

Reduction of EUV resist damage by neutral beam etching

Even though EUV lithography has the advantage of implenting a finer pattern compared to ArF immersion lithography due to the use of 13.5 nm instead of 193 nm as the wavelength of the light source, due to the low energy of EUV light source, EUV resist has a thinner thickness than conventional ArF resist. EUV resist having such a thin thickness is more vulnerable to radiation damage received during the etching because of its low etch resistance and also tends to have a problem of low etch selectivity. In this study, the radiation damage to EUV resist during etching of hardmask materials such as Si3N4, SiO2, etc using CF4 gas was compared between neutral beam etching (NBE) and ion beam etching (IBE). When NBE was used, after the etching of 20 nm thick EUV resist, the line edge roughness increase and the critical dimension change of EUV resist were reduced by ∼1/3 and ∼1/2, respectively, compared to those by IBE. Also, at that EUV etch depth, the root mean square surface roughness value of EUV resist etched by NBE was ∼2/3 compared to that by IBE on the average. It was also confirmed that the etching selectivity between SiO2, Si3N4, etc and EUV resist was higher for NBE compared to IBE. The less damage to the EUV resist and the higher etch selectivity of materials such as Si3N4 and SiO2 over EUV resist for NBE compared to IBE are believed to be related to the no potential energy released by the neutralization of the ions during the etching by NBE.

Pattern collapse mitigation by controlling atmosphere during development process for semiconductor lithography

The negative pressure atmosphere during the development process was investigated to mitigate the photoresist pattern collapse which is one of the traditional issues in the lithography processes for every generation of photoresists; i-line, KrF, ArF, ArF immersion, and recently extreme ultraviolet. The pattern collapse is caused by the capillary force between resist patterns during rinsing and drying in the development process. The main factors of capillary force are the surface tension and the contact angle of rinsing liquid and also the pattern structure (line width, space width, and height). On the other hand, the capillary force is influenced by the atmosphere pressure. In this paper, we controlled the chamber pressure during the rinsing and drying processes for the pattern collapse mitigation. The minimum critical dimension without pattern collapse under the negative pressure was found to be smaller (approximately 10% improvement) than that obtained with atmosphere pressure.

Effects of mask pattern transmission on ArF lithographic performance in contact hole patterning

Even with the increase in need for next-generation lithography, immersion ArF lithography is still applied to the majority of critical layers. However, as circuit designs shrink, conventional 6% phase-shift mask (PSM) will become difficult to meet the lithography requirements for dense dot pattern compared to dense line pattern. To enhance immersion ArF lithographic performances for dot pattern, high-transmission PSM (High-T PSM) is attracting attention because the transmission of PSM has a significant impact on lithographic performances. From results of transmission dependency evaluated by mask three-dimensional (3D) simulation, it was found that 30% transmission has the best lithographic performances for dense dot. Based on these results, mask blank and mask making process for the new 30% PSM were developed. The results showed good cross-section profile, mask pattern resolution, and defect repairability. In addition, the durability against chemical cleaning and ArF irradiation were also improved. Wafer printability test using negative tone development demonstrated that new PSM has advantages in process window and mask error enhancement factor for dense dots (holes on wafer). Finally, the potential for further application of new PSM was investigated by mask 3D simulation. The results showed that new PSM has lithographic benefits not only for dense dots but also other patterns.

Application of ethyltrimethylammonium hydroxide (ETMAH) as an alternative developer solution/process for semiconductor lithography

Investigations were made on the application of aqueous ethyltrimethylammonium hydroxide (ETMAH) as an alternative developer solution (compared to the de facto standard aqueous tetramethylammonium hydroxide or TMAH) for mainstream lithographic technologies; extreme ultraviolet (EUV), ArF immersion (ArFi), KrF, and i-line. Results show that for EUV, ETMAH at a specific developer concentration allows mitigation of resist-based stochastic defects while maintaining lithographic performance. It was also found that the ETMAH developer solution is compatible with the ArFi, KrF, and i-line lithography (ultimate resolution and line width roughness was maintained). For EUV, ArFi, and KrF lithography which utilizes chemical amplification resist (CAR) material platforms, sensitivity remained constant. For i-line lithography, sensitivity was observed to decrease by roughly 25%–30% when ETMAH was utilized, attributed to the different dissolution mechanism of the novolac-based resist compared to CAR. Nevertheless, these results show the viability of ETMAH as an alternative developer solution for mainstream semiconductor lithography.

Self-aligned double patterning for active trim contacts with anisotropic pattern pitches in sub-20 nm dynamic random access memories

Background: With continuous decrease in the technology node of dynamic random access memories (DRAMs) down to sub-20 nm, the self-aligned double patterning (SADP) is an effective approach to generate two-dimensional (2-D) patterns, particularly contact arrays. Aim: We demonstrate a patterning scheme using the SADP technique to produce active trim contacts with anisotropic pattern pitches. Approach: The proposed scheme uses two consecutive spacer-formation processes. Results: By making the ellipsoidal core pillars and minimizing the spacer thickness, 2-D critical dimensions (CDs) for self-generated contacts match well with those for core contacts. In addition, an interesting cross-dependence of X -CD and Y -CD variations for the core and self-generated contacts is observed. Conclusion: This patterning approach is useful for forming active trim contacts in sub-20 nm DRAMs using fewer numbers of ArF immersion photolithography steps.

(Invited) Cavity-Free Micro Thermoelectric Energy Harvester with Si Nanowires

Forthcoming trillion-sensors-network society demands the maturity of energy harvesting technology. Among various energy harvesting devices, thermoelectric generator (TEG), which utilizes the Seebeck effect of semiconductors, is anticipated as an ultimate one because it has a potential to provide a semipermanent power from almost unlimited heat energies. In a TEG, the efficiency of energy conversion from heat to electricity is determined by the thermoelectric figure of merit, ZT= S2σT/κ of the employed semiconductor, where S is the Seebeck coefficient, σ the electrical conductivity, κ the thermal conductivity, and T the average temperature between heat source and cold sink. Although higher ZT is favorable to achieve high conversion efficiency, only limited materials were known to have high ZT near the room temperature. Recently, silicon nanowires (Si-NWs) emerged as a promising thermoelectric material; the thermal conductivity of Si-NW was found to decrease drastically as the nanowire is thinned. [1,2] Since then, a number of fabrication examples of Si-based TEG has been reported. [3-5] Conventional demonstrations of planar type Si-based TEG employed long Si-NWs about 10-100 μm which were suspended on a cavity to avoid the bypass of the heat current, as shown in Fig 1a. The authors’ group proposed a new design of planar and short Si-NW TEG, which is illustrated as Fig. 1b. [6-9] Our proposed device is driven by a steep temperature gradient exuding around a heat flow perpendicular to the substrate, and the nanowires are not suspended on a cavity. Furthermore, the power density is scalable by shortening Si-NW to sub-μm length; the areal power generation density is inversely proportional to the square of the NW length. It has been experimentally confirmed that the thermoelectric power was enhanced by shortening the nanowire, and tens of µW/cm2-class power generation was achieved [6,7]. Fig. 2 shows an experimental Si-NW TEG fabricated on a silicon-on-insulator (SOI) wafer by the conventional CMOS process. The SOI layer was patterned into Si-NWs by ArF immersion lithography and reactive-ion etching. Both ends of Si-NW bundle are connected to Si-pads. Al/TiN/Ti electrode was deposited on the Si-pad. We prepared samples with different base Si-substrate thickness, by thinning with backside grinding. The hot side electrode was heated by a custom-made micro thermostat, and the base stage was maintained at room temperature by a water chiller. Fig. 3 shows the thermoelectric power density versus loading voltage curves, measured under an applied external temperature difference of 5 K. The measured power output is normalized by the area of the product of twice of the NW length and the NW pitch, supposing that the pads and NW arrays have a same footprint. The maximum power is obtained in the shortest NW device with 0.25 µm long. The thermoelectic power was drastically enhanced by reducing the Si-substrate thickness. Fig. 4 shows the dependence of the power density on the Si-substrate thickness. The power density of a sample with 50 µm thick Si-substrate reached 12 µW/cm2. The enhancement can be attributed to the increased temperature difference across Si-NWs by suppression of the series thermal resistance at the Si-substrate. Further improvement of thermoelectic power is expected by suppressing the thermal resistance at the Si-substrate. The temperature difference across Si-NW is expected to increase by partially replacing the Si substrate underneath the cold side edge of SiNW with Cu with higher thermal conductivity. According to our finite-element-simulation, [10] however, not only beneath the cold side edge of SiNW, replacing the whole substrate by Cu is the most effective way to improve the power generation density (Fig. 5). The results show that the thermal resistance of the entire substrate should be suppressed as a matter of first priority.

Placement of Sub-Resolution Assist Features Based on a Genetic Algorithm

Resolution enhancement techniques compatible with an ArF (193 nm) immersion optical lithography system may constitute an effective means of minimizing the size of technology nodes of the dynamic random access memory. This paper investigated one such technique, namely mask optimization (MO), and applied sub-resolution assist features (SRAFs) in the MO to improve the aerial image quality of a target pattern that had undergone optical proximity correction (OPC). This paper first developed an optical model based on the Hopkins model to create an interference map, which was then used to create a cut-level map. The cut-level map was instrumental in predicting potential SRAF sites and randomly generating SRAFs that would serve as the initial population for a genetic algorithm (GA). Chromosomes were defined as a section map and encoded genes were used to define SRAF and target pattern. Using a GA to identify SRAF geometric measurements and placement was revealed to increase the process window and improve the image performance of the target pattern. This paper used 1D and 2D line/space (L/S) images as the baseline to test the convergence of the proposed method. 2D images were also used to test improvements in aerial image performance. The results indicated that the 1D L/S pattern converged at the 100th iteration. Furthermore, the depths of the focus of the 2D L/S array and 2D contact hole patterns were successfully increased by 113 and 21 nm, respectively. The proposed SRAF method, which integrated the GA and interference map, was able to ensure the diversity of potential SRAF solutions. Moreover, it was able to restrict the SRAF solutions to rectangular structures through the application of mask rules, thereby reducing the cost and improving the feasibility of photomasks.

Low-Insertion-Loss and Power-Efficient 32 × 32 Silicon Photonics Switch With Extremely High-Δ Silica PLC Connector

We fabricate a 32 × 32 silicon photonics switch on a 300-mm silicon-on-insulator wafer by using our complementary metal-oxide-semiconductor pilot line equipped with an immersion ArF scanner and demonstrate an average fiber-to-fiber insertion loss of 10.8 dB with a standard deviation of 0.54 dB, and on-chip electric power consumption of 1.9 W. The insertion loss and the power consumption are approximately 1/60, and less than 1/4 of our previous results, respectively. These significant improvements are achieved by design and fabrication optimization of waveguides and intersections on the chip, and by employing a novel optical fiber connector based on extremely-high-Δ silica planar-lightwave-circuit (PLC) technology. The minimum crosstalk was −26.6 dB at a wavelength of 1547 nm, and −20-dB crosstalk bandwidth was 3.5 nm. Furthermore, we demonstrate low-crosstalk bandwidth expansion by using output port exchanged element switches. We achieve a −20 dB crosstalk bandwidth of 14.2 nm, which is four-times wider than that of the conventional element switch based 32 × 32 switch.

Novel Fast Etch Rate BARC for ArF Immersion Lithography

Novel Fast Etch Rate BARC for ArF Immersion Lithography

Demonstration of ACO-Based Freeform Source for ArF Laser Immersion Lithography System

This paper describes the use of ArF immersion lithography to verify the feasibility of a self-developed freeform illumination source that exposes features on masks and forms resist patterns. After development inspection (ADI) was used to measure the results and inspect whether the critical dimension (CD), process window, line-edge roughness (LER), and line-width roughness (LWR) of the resist pattern attained the standards of existing manufacturing processes. The testing features include nine horizontal and eight vertical features. Ant colony optimization (ACO) can provide optimal freeform illumination sources for these horizontal and vertical features. This paper considers each feature’s particular weighting in order to test the complexity and adaptability of the ACO algorithm applied to semiconductor manufacturing processes. The results of source calculations show that all 17 testing features can be satisfied with the X symmetry freeform source. When using this freeform source in an ArF lithography system, the ADI resist CD of all testing features is located within ±10% target CD tolerance. The ADI target CD set by dense patterns is 40 nm. Resist pattern ADI CD measurements show that, under a through-focus condition, the resist pattern CD between 40 and 42 nm is within tolerance, the depth of focus can reach up to $0.1~\mu \text{m}$ , LER is approximately 5 nm, and LWR is approximately 7 nm. These ADI CD measurements show that this ACO-based freeform source can be integrated into existing advanced semiconductor lithography processes.

Extreme ultraviolet resist materials for sub-7 nm patterning.

Continuous ongoing development of dense integrated circuits requires significant advancements in nanoscale patterning technology. As a key process in semiconductor high volume manufacturing (HVM), high resolution lithography is crucial in keeping with Moore's law. Currently, lithography technology for the sub-7 nm node and beyond has been actively investigated approaching atomic level patterning. EUV technology is now considered to be a potential alternative to HVM for replacing in some cases ArF immersion technology combined with multi-patterning. Development of innovative resist materials will be required to improve advanced fabrication strategies. In this article, advancements in novel resist materials are reviewed to identify design criteria for establishment of a next generation resist platform. Development strategies and the challenges in next generation resist materials are summarized and discussed.

Enhanced Cleaning for the Point-of-Use Filter and its Effectiveness on Wafer Defectivity in Immersion ArF Lithography Process

Enhanced Cleaning for the Point-of-Use Filter and its Effectiveness on Wafer Defectivity in Immersion ArF Lithography Process

Low-loss silicon wire waveguides for optical integrated circuits

Abstract

The impacts of fabrication error in Si wire-waveguides on spectral variation of coupled resonator optical waveguides

We experimentally investigate the impacts of fabrication error in Si wire-waveguides on the spectral variation of 5th-order coupled resonator optical waveguides (CROWs). In the fabrication of these waveguide devices, 40-nm-node CMOS technology with ArF immersion lithography was used. The characterization of the CROWs was done by using an automatic optical wafer-level probing system. As for the fabrication errors in 440-nm-wide/220-nm-thick waveguides, standard deviations in waveguide cross-sectional size for a single 300-mm wafer were confirmed to be 0.83nm in width and 0.24nm in height. The fabricated CROWs in a single wafer exhibited quite similar resonant peak shapes to each other, and also showed a remarkably small standard deviation of 0.67nm in resonant wavelength, which agrees with the theoretical estimation from the fabrication error. These results show that the precise process control using ArF immersion lithography technology is effective to the reproducible device fabrication for wide-bandwidth optical interconnection.

Theoretical study of fabrication of line-and-space patterns with 7 nm quarter-pitch using electron beam lithography with chemically amplified resist process: III. Post exposure baking on quartz substrates

Electron beam (EB) lithography is a key technology for the fabrication of photomasks for ArF immersion and extreme ultraviolet (EUV) lithography and molds for nanoimprint lithography. In this study, the temporal change in the chemical gradient of line-and-space patterns with a 7 nm quarter-pitch (7 nm space width and 21 nm line width) was calculated until it became constant, independently of postexposure baking (PEB) time, to clarify the feasibility of single nano patterning on quartz substrates using EB lithography with chemically amplified resist processes. When the quencher diffusion constant is the same as the acid diffusion constant, the maximum chemical gradient of the line-and-space pattern with a 7 nm quarter-pitch did not differ much from that with a 14 nm half-pitch under the condition described above. Also, from the viewpoint of process control, a low quencher diffusion constant is considered to be preferable for the fabrication of line-and-space patterns with a 7 nm quarter-pitch on quartz substrates.