(Invited) Cavity-Free Micro Thermoelectric Energy Harvester with Si Nanowires

Abstract

Forthcoming trillion-sensors-network society demands the maturity of energy harvesting technology. Among various energy harvesting devices, thermoelectric generator (TEG), which utilizes the Seebeck effect of semiconductors, is anticipated as an ultimate one because it has a potential to provide a semipermanent power from almost unlimited heat energies. In a TEG, the efficiency of energy conversion from heat to electricity is determined by the thermoelectric figure of merit, ZT= S2σT/κ of the employed semiconductor, where S is the Seebeck coefficient, σ the electrical conductivity, κ the thermal conductivity, and T the average temperature between heat source and cold sink. Although higher ZT is favorable to achieve high conversion efficiency, only limited materials were known to have high ZT near the room temperature. Recently, silicon nanowires (Si-NWs) emerged as a promising thermoelectric material; the thermal conductivity of Si-NW was found to decrease drastically as the nanowire is thinned. [1,2] Since then, a number of fabrication examples of Si-based TEG has been reported. [3-5] Conventional demonstrations of planar type Si-based TEG employed long Si-NWs about 10-100 μm which were suspended on a cavity to avoid the bypass of the heat current, as shown in Fig 1a. The authors’ group proposed a new design of planar and short Si-NW TEG, which is illustrated as Fig. 1b. [6-9] Our proposed device is driven by a steep temperature gradient exuding around a heat flow perpendicular to the substrate, and the nanowires are not suspended on a cavity. Furthermore, the power density is scalable by shortening Si-NW to sub-μm length; the areal power generation density is inversely proportional to the square of the NW length. It has been experimentally confirmed that the thermoelectric power was enhanced by shortening the nanowire, and tens of µW/cm2-class power generation was achieved [6,7]. Fig. 2 shows an experimental Si-NW TEG fabricated on a silicon-on-insulator (SOI) wafer by the conventional CMOS process. The SOI layer was patterned into Si-NWs by ArF immersion lithography and reactive-ion etching. Both ends of Si-NW bundle are connected to Si-pads. Al/TiN/Ti electrode was deposited on the Si-pad. We prepared samples with different base Si-substrate thickness, by thinning with backside grinding. The hot side electrode was heated by a custom-made micro thermostat, and the base stage was maintained at room temperature by a water chiller. Fig. 3 shows the thermoelectric power density versus loading voltage curves, measured under an applied external temperature difference of 5 K. The measured power output is normalized by the area of the product of twice of the NW length and the NW pitch, supposing that the pads and NW arrays have a same footprint. The maximum power is obtained in the shortest NW device with 0.25 µm long. The thermoelectic power was drastically enhanced by reducing the Si-substrate thickness. Fig. 4 shows the dependence of the power density on the Si-substrate thickness. The power density of a sample with 50 µm thick Si-substrate reached 12 µW/cm2. The enhancement can be attributed to the increased temperature difference across Si-NWs by suppression of the series thermal resistance at the Si-substrate. Further improvement of thermoelectic power is expected by suppressing the thermal resistance at the Si-substrate. The temperature difference across Si-NW is expected to increase by partially replacing the Si substrate underneath the cold side edge of SiNW with Cu with higher thermal conductivity. According to our finite-element-simulation, [10] however, not only beneath the cold side edge of SiNW, replacing the whole substrate by Cu is the most effective way to improve the power generation density (Fig. 5). The results show that the thermal resistance of the entire substrate should be suppressed as a matter of first priority.