Area Efficient Design Research Articles

Two CMOS LNAs Sharing the Same On-Chip Inductors and Bias Network

An area-efficient design for two 2.4 GHz CMOS LNAs is presented, by sharing the on-chip inductors and bias network. Compared with LNA1, LNA2 features a new technique to improve the linearity of CMOS LNA, achieving a much higher IIP3 with the tradeoff of voltage gain and noise figure.

Systolic array for the fast age (alternating group explicit) method for parabolic equations (safage)

In this paper a simpler and more area efficient design for the solution of parabolic equations by systolic array computation is presented. The design is an improvement on previous designs as it reduces the control and computation cycle time of the basic cells by using certain simplifications of the AGE scheme. The resulting design is suitable for a VLSI hard-systolic algorithm and possible implementation as chips.

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.

High-bandwidth high-accuracy rotary microactuators for magnetic hard disk drive tracking servos

Reports on the design, fabrication, and testing of an electrostatic microactuator for a magnetic hard disk drive (HDD) tracking servo. The design requirements for a microactuator are investigated. These include high Z-directional stiffness, low in-plane stiffness, high structural aspect ratio, large output force, high area efficiency, low cost, and mass batch production. An area-efficient rotary microactuator design was devised, and microactuators were successfully fabricated using innovative processing technologies. The microactuator has a structural thickness of 40 /spl mu/m with a minimum gap/structure width of approximately 2 /spl mu/m. Its frequency response was measured and it was determined that it can be modeled as a second-order linear system, up to the 26-kHz frequency range. Moreover, the microactuator will enable the design of a servo system that exceeds a 5-kHz servo bandwidth, which is adequate to achieve a track density of more than 25 kilotrack per inch (kTPI). The microactuator/slider assembly was also tested on a spinning disk, with its position controlled by a PID controller using the magnetic position error signal written on the disk. An accuracy of about 0.05 /spl mu/m was observed when the servo controller was turned on. Continuous-time dual-stage servos were designed and simulated using the /spl mu/-synthesis technique. A sequentially designed SISO and a MIMO control design method have been shown to be capable of meeting prescribed uncertainty and performance specifications.

Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits

In this paper we develop dynamic models for ideal three- and four-stage voltage multipliers. Starting from the models proposed, we can perform a pencil-and-paper area-efficient optimized design. The circuits discussed are commonly used in power ICs or memory ICs to allow the switching on of an MOS device. The models proposed are validated both by measurement on a breadboard and by SPICE simulation.

Comments on "High-speed area-efficient multiplier design using multiple-valued current-mode circuits"

S. Kawahito et al. (1988) presented multiplier designs using the binary-tree reduction feature of certain highly redundant radix-2 representations, along with multiple-valued current-mode circuit techniques, and shown them to compare favorably to those based on less redundant binary signed-digit and carry-save numbers. We point out that these representation schemes, and their potential advantages, have been discussed in earlier publications and that a more general view of the parallel-carries addition process exploited in these multipliers leads to other potentially useful representations. The authors reply is also given.

Design and fabrication of microactuators for high density data storage

The design and fabrication of mm-sized MEMS actuator structures is described. A one-mm-sized microfabricated actuator is capable of linearized output of 0.2 mN when driven at 60 Volts by using an area-efficient electrostatic design, a high-aspect ratio microfabrication process, and a large signal linearization scheme. This increased output force enables the batch-fabricated microactuators to be used in practical applications in which the microactuators are required to move an external load. This paper concentrates on the design and process issues of the microactuators used as the fine actuator in a two-stage servo system for the high bandwidth positioning of a magnetic recording head slider. Other devices made by the same process technology are fully-integrated wobble micromotors and wobble actuators with potential applications in chip-sized disk drives using tip-based high density data storage.

Area efficient systolic interconnection networks

Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is particularly applicable for high wire organisations typically used in interconnection networks. In the paper, it is shown that classical cross-bar type interconnection networks, formed as systolic arrays, have better composite VLSI performance metrics than most popular interconnection networks that use high wire organisations even though systolic organisations have the disadvantage of being larger in terms of silicon area. The authors outline a new, hybrid architecture for interconnection networks that trades speed advantages of systolic arrays with area advantages of high wire organisations. An implementation, in VLSI, of a butterfly network using the proposed approach is described, and it is shown why this is useful in designing an area efficient interconnection network.

Integrated multilayer high aspect ratio milliactuators

Abstract We report here an integrated multilayer high aspect ratio process, and mm-sized electromechanical actuator structures fabricated by this process. The high aspect ratio microfabrication process allows the generation of structures an order of magnitude larger than conventional structures in all three dimensions, while still retaining the minimum in-plane features. We will describe a detailed example of a 1-mm-sized microfabricated actuator with a linearized output capability of 0.2 mN when driven at 60 V. In addition to the high aspect ratio microfabrication process, the high force output is achieved through an area-efficient design and a large-signal linearization scheme. The area-efficient design allows full utilization of the chip area for energy conversion. The large-signal linearization scheme permits a linearized force output with driving voltages as large as the biasing voltage. This increased output force enables the batch-fabricated microactuators to be used in many new, practical applications in which the microactuators are required to move an additional load as well as their own mass. Other structures made possible by this process are fully-integrated wobble micromotors with notched pin-joints for extended high aspect ratio gaps between rotors, stators and axles.

Efficient VLSI implementation of iterative solutions to sparse linear systems

We propose a novel way of solving systems of linear equations with sparse coefficient matrices using iterative methods on a VLSI array. The nonzero entries of the coefficient matrix are mapped onto a processor array of size √ e × √ e, where e is the number of nonzero elements, n is the number of equations and e ⩾ n. The data transport problem that arises because of this mapping is solved using an efficient routing technique. Preprocessing is carried out on the iteration matrix of the system to compute the routing control-words that are used in the data transfer. This results in O(√ e) time for each iteration of the method, with a small constant factor. As compared to existing VLSI methods for solving the problem, the proposed method yields a superior time performance, greater ease of programmability and an area efficient design. We also develop a second implementation of our algorithm that uses a slightly higher number of communication steps, but reduces the number of arithmetic operations to O(log e). The latter algorithm is suitable for many other architectures as well. The algorithm can be implemented in O(log e) time using e processors on a hypercube, shuffle-exchange, and cube-connected-cycles.

Shortening the design cycle for programmable logic

X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis. >

Programmable multiplexed switched-capacitor filters

An area-efficient design approach for implementing a fully programmable Nth order switched-capacitor filter is proposed. Since programmable capacitor arrays (PCAs) consume vast amounts of area the proposed approach makes use of time-multiplexing resulting in the need for only three PCAs.