Digital Signal Processing Architectures Research Articles

Runtime Partial Reconfiguration of FPGAs for DSP Applications

This paper presents a novel partially reconfigurable FIR filter design for varied and wide range of DSP applications, which employ dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters using Xilinx FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This FIR filter design method shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

Power Comparison of CMOS and Adiabatic Full Adder Circuits

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

A low power clock generator with adaptive inter-phase charge balancing for variability compensation in 40-nm CMOS

Abstract. Power dissipation besides chip area is still one main optimization issue in high performance CMOS design. Regarding high throughput building blocks for digital signal processing architectures which are optimized down to the physical level a complementary two-phase clocking scheme (CTPC) is often advantageous concerning ATE-efficiency. The clock system dissipates a significant part of overall power up to more than 50% in some applications. One efficient power saving strategy for CTPC signal generation is the charge balancing technique. To achieve high efficiency with this approach a careful optimization of timing relations within the control is inevitable. However, as in modern CMOS processes device variations increase, timing relations between sensitive control signals can be affected seriously. In order to compensate for the influence of global and local variations in this work, an adaptive control system for charge balancing in a CTPC generator is presented. An adjustment for the degree of charge recycling is performed in each clock cycle. In the case of insufficient recycling the delay elements which define duration and timing position of the recycling pulse are corrected by switchable timing units. In a benchmark with the conventional clock generation system, a power reduction gain of up to 24.7% could be achieved. This means saving in power of more than 12% for a complete number-crunching building block.

A Strict-Time Distributed Architecture for Digital Beamforming of Ultrasound Signals

This paper presents a strict timing-coherent digital signal processing architecture. The main requirement is that programmable events can be produced within predictable time intervals with tight accuracy (timing errors <; 1 ns). This characteristic is essential to ultrasound beamforming. The followed approach defines a modular and scalable architecture (AMPLIA), which is configured as a multibranch pipeline. This arrangement guarantees timing coherence along all the system, independent of the number of processing modules. An important element of the architecture is the interface and control unit (ICU), which decouples the asynchronous communication channel with a host computer to the strictly timing-coherent domain of the signal processing system. Furthermore, in the beamforming application, several elements have a great impact on system timing resolution, particularly when dynamic focusing is involved. This paper addresses the issues of coded excitation, analog-to-digital (A/D) conversion, and signal interpolation in achieving dynamic focusing by progressive focusing correction with processing rates of several gigasamples per second and tight timing accuracy.

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.

Readout system of the ALICE Muon tracking detector

A Large Ion Collider Experiment (ALICE) will be aimed at studying heavy ion collisions at the extreme energy densities accessible at the CERN's Large Hadron Collider (LHC), where the formation of the Quark Gluon Plasma is expected. The ALICE muon forward spectrometer will identify muons with momentum above 4GeV/c, allowing the study of quarkonia and heavy flavors in the pseudorapidity range −4.0<η<−2.5 with 2π azimuthal coverage. The muon tracking system consists of 10 Cathode Pad Chambers (CPC) with 1.1 million of pads that represent the total number of acquisition channels to manage.In this article, we will give an overview of the ALICE Muon Spectrometer. Afterward, we will focus on tracking system Front end Electronics (FEE) and readout system. We will show that the Digital Signal Processor (DSP) architecture fulfills all the requirements, including radiation hardness against neutrons. Finally, real-time performances are discussed.

Reduced complexity analogue-to-residue conversion employing folding number system

Digital signal processing (DSP) algorithms are computationally intensive and require recursive multiplication and addition. Residue number systems (RNS) offer significant advantages over conventional number systems when used in the design of special purpose DSP architectures. However, conversion of analogue signals into their residue equivalents requires first converting the signal to binary equivalents and subsequently using modular circuits to convert the resultant binary to residues. A new number system called the folding number system (FNS) is proposed and used as the basis for residue conversion. Since FNS has one-to-one correspondence with RNS, the proposed method converts the analogue signal to its RNS equivalents using concealed symmetrical residues in FNS domain. The conversion is simple and uses analogue folding circuits, comparators and combinatorial logic circuits. High-frequency analogue signals can be efficiently converted thus enabling RNS to be implemented in high-speed signal processing architectures.

Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. The target power consumption is 100 μW as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of 11 μW is possible for both radio and DSP running the electrocardiogram algorithm.

Power estimation technique for DSP architectures

The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block's primary inputs. In experiments with the DSP system, the average error is 26%.

Ultrahigh-Speed Optical Correlation System Using Holographic Disc

The volume of information we handle is markedly increasing as a result of the change from text data to still and moving image files. In this paper, we propose and describe fabrication of a much higher speed search engine for image and video data using a holographic optical disc system. Preliminary correlation experiments using the holographic optical disc setup show an excellent performance as indicated by high correlation peaks and low error rates at a multiplexing pitch of 10 µm, and a rotational speed of 300 rpm. It is clear that the processing speed of our optical holographic calculation is markedly higher than the conventional digital signal processing architecture. This system can also be applied to various search engine systems.

Introduction to the Special Issue on SAMOS 2007

This special issue includes a selection of the best papers from the 2007 SAMOS VII Symposium. The International Symposium on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS) is an event which annually takes place on the scenic Mediterranean island of Samos. It comprises two co-located events—the International SAMOS Conference and the SAMOS Workshop. In 2007 more than 200 papers were submitted for these two events. After a very competitive selection process only about 30% of these papers have been selected for presentation. According to the Symposium’s ranked results and the results of a second stage review process of all presentations from SAMOS, the following eight papers related to architectures and implementations of embedded systems have been selected for publication in this special issue. We would like to thank all reviewers of the SAMOS Workshop and particularly all reviewers of this special issue for their detailed and intensive review work. The investment of their time and insight is very much appreciated and helped to generate this selection of high quality technical papers. The important field of Digital Signal Processor Architectures which is classically one of the focus topics of SAMOS is covered in this special issue by three papers: Thuresson et al. present a paper which is entitled “FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.” Within this paper the authors present a highly efficient DSP architecture and discuss specific elements of this architecture including fine-grained control and a flexible interconnect which lead to significant speedups and significant energy savings. They elaborated on their flexible interconnect that allows the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore provides specialized datapath units to be inserted and utilized within the same architecture and compilation framework. The problem of memory bottlenecks in modern DSP architectures is addressed by the paper of Pitkaenen et al. which is entitled “Parallel Memory Architecture for Application-Specific Instruction-Set Processors.” In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed parallel memory system is attached to an ASIP core and comparisons on area, power, and critical path are presented. Significant power savings can be obtained by exploiting their parallel memory system instead of multi-port memories. Memory access problems are also addressed in the paper of Galuzzi et al. In “High-bandwidth Address Generation Unit” they present an efficient data fetch circuit to retrieve several operands from an n-way interleaved memory system in a single machine cycle. The proposed address generation unit operates with an improved version of a low-order interleaved memory access approach. The presented design supports data structures of arbitrary lengths and various odd strides. J Sign Process Syst (2009) 57:1–3 DOI 10.1007/s11265-008-0220-8

Event detection intelligent camera development

A new camera system ‘event detection intelligent camera’ (EDICAM) is being developed for the video diagnostics of W-7X stellarator, which consists of 10 distinct and standalone measurement channels each holding a camera. Different operation modes will be implemented for continuous and for triggered readout as well. Hardware level trigger signals will be generated from real time image processing algorithms optimized for digital signal processor (DSP) and field programmable gate array (FPGA) architectures. At full resolution a camera sends 12 bit sampled 1280 × 1024 pixels with 444 fps which means 1.43 Terabyte over half an hour. To analyse such a huge amount of data is time consuming and has a high computational complexity. We plan to overcome this problem by EDICAM's preprocessing concepts. EDICAM camera system integrates all the advantages of CMOS sensor chip technology and fast network connections. EDICAM is built up from three different modules with two interfaces. A sensor module (SM) with reduced hardware and functional elements to reach a small and compact size and robust action in harmful environment as well. An image processing and control unit (IPCU) module handles the entire user predefined events and runs image processing algorithms to generate trigger signals. Finally a 10 Gigabit Ethernet compatible image readout card functions as the network interface for the PC. In this contribution all the concepts of EDICAM and the functions of the distinct modules are described.

Optimized address assignment with array and loop transformations for minimizing schedule length

Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, address operation reduction rotation scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.

A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW–SIMD DSP

We implemented the H.264/AVC variable block size motion estimation (VBSME) using a very long instruction word (VLIW)---single instruction multiple data (SIMD) digital signal processor (DSP). The SAD_Reuse method which has a regular structure is chosen for VBSME not only to remove redundant sum of absolute difference (SAD) operations but also to utilize the instruction level parallelism (ILP) and data level parallelism (DLP) of the architecture. A fast mode decision algorithm is developed to reduce the number of `compare and update' operations and simplify the rate distortion optimization (RDO). The developed fast mode decision uses the difference of motion vectors and the maximum a posteriori (MAP) estimation of the rate-distortion costs. Several advanced software techniques that include software pipelining and packed-data processing are employed. Especially, memory access overhead reduction schemes including the multi-block processing and the inter-procedural scheduling are used for the software optimization. In order to reduce the `write buffer full' in the quarter pixel ME, a 4 bit quantization scheme is developed, which increases the number of arithmetic operations but decreases the stall cycles very much. The implemented variable block size ME for H.264/AVC requires an average of 9 M and 78 Mcycles per frame for QCIF and CIF size video sequences, respectively, in the TMS320C64x DSP architecture.

Optimize Address Assignment With Array and Loop Transformations for Minimizing Schedule Length

Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, address operation reduction rotation scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.

High-level FSMD design and automated clock gating with CoDeL

A high-level VLSI design platform, called CoDeL, which allows hardware description at the algorithm level and thus dramatically reduces design time, is presented. It now directly supports the use of fixed-point operations to ease description of digital signal processing (DSP) algorithms. Also, to dramatically reduce dynamic power dissipation in the resulting architecture, it automatically inserts clock gating for registers at the behavioural level. This is believed to be the first hardware design environment that allows an algorithmic description of a component and yet produces a power-aware design. The DSP stone benchmark is used to thoroughly evaluate this fixed-point design platform for the design of power-efficient DSP architectures. Power analysis is used to compare the effectiveness of CoDeL's automated clock gating to automated clock gating using Synopsys tools. The results show that a combination of CoDeL and Synopsys clock gating provides 16% more power savings, on average, than Synopsys' automated clock gating alone. Finally, the CoDeL platform is compared to a modern DSP processor, and it is found that the CoDeL platform produces designs with somewhat slower run times, but dramatically lower power dissipation.

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.

An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architecture

To meet ever-increasing demands for higher performance and lower power consumption, many high-end digital signal processors (DSPs) commonly employ non-orthogonal architecture. This architecture typically is characterized by irregular data paths, heterogeneous registers, and multiple memory banks. Moreover, sufficient compiler support is obviously important to harvest its benefits. However, usual compilation techniques do not adapt well to non-orthogonal architectures and the compiler design becomes much more difficult due to the complexity of these architectures. The entire code generation process for non-orthogonal architecture must include several phases. In this paper, we extend our previous study to propose a code generation algorithm Rotation Scheduling with Spill Codes Avoiding ( RSSA), which is suitable for various DSPs with similar architectural features. As well as introducing detailed principles and algorithms of RSSA, we select several DSP applications and evaluate it under Motorola DSP56000 architectures. The evaluation results clearly demonstrate the effectiveness of RSSA, which can obtain scheduling results with minimum length and fewer spill codes compared to related work. In addition, in order to study the influence of different number of resources on the scheduling result, we also define a hypothetical machine model to represent a scalable non-orthogonal DSP architecture. After evaluating RSSA on various target architectures, we find that adding additional accumulators is the most efficient way to reduce spill codes. Meanwhile, for instruction-level parallelism exploration, numbers of data ALUs and accumulators have to be concurrently increased. Furthermore, based on our analysis, RSSA is not only effective but also quite efficient compared to related studies.