Digital Signal Processing Architectures Research Articles

A two-level reconfigurable architecture for digital signal processing

This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 4 × 4 matrix of smaller “elements” to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-μm CMOS technology. Circuit simulations of the cell in 0.25-μm technology indicate that the design achieves a clock frequency of 200 MHz.

A 3-D Baseband Signal Analyzer Prototype for 3G Mobile Telecommunication Systems

The paper deals with the realization of a new instrument for the qualification of third-generation (3G) mobile telecommunication systems. It is based on the parallel computing of a time-frequency representation called smoothed pseudo-Wigner-Ville distribution (SPWVD) on a multiple digital signal processor architecture. The SPWVD allows the performance of signal analysis simultaneously in both the time and frequency domain. The hardware and software implementations of the instrument prototype are presented and discussed. Then, the first validation results, obtained on wide-band code-division-multiplexing access (W-CDMA) signals compliant with the 3rd Generation Partnership Program (3GPP) standard, are reported.

A real-time multitarget tracking system with robust multichannel CNN-UM algorithms

This paper introduces a tightly coupled topographic sensor-processor and digital signal processor (DSP) architecture for real-time visual multitarget tracking (MTT) applications. We define real-time visual MTT as the task of tracking targets contained in an input image flow at a sampling-rate that is higher than the speed of the fastest maneuvers that the targets make. We utilize a sensor-processor based on the cellular neural network universal machine architecture that permits the offloading of the main image processing tasks from the DSP and introduces opportunities for sensor adaptation based on the tracking performance feedback from the DSP. To achieve robustness, the image processing algorithms running on the sensor borrow ideas from biological systems: the input is processed in different parallel channels (spatial, spatio-temporal and temporal) and the interaction of these channels generates the measurements for the digital tracking algorithms. These algorithms (running on the DSP) are responsible for distance calculation, state estimation, data association and track maintenance. The performance of the proposed system is studied using actual hardware for different video flows containing rapidly moving maneuvering targets.

Efficient assignment and scheduling for heterogeneous DSP systems

This paper addresses high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an important problem is how to assign a proper FU type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve the heterogeneous assignment problem, i.e., how to assign proper FU types to applications such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained in the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove that the heterogeneous assignment problem is NP-complete. Efficient algorithms are proposed to find an optimal solution when the given DFG is a simple path or a tree. Three other algorithms are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost compared with the previous work.

Implementing an OFDM receiver on the RaPiD reconfigurable architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications that require a combination of high performance, low cost, and flexibility. Unfortunately, the use of FPGAs in mobile embedded systems platforms is hampered by the very large overhead of FPGA-based architectures. Coarse-grained configurable architectures can reduce this overhead substantially by taking advantage of the application domain to specialize the reconfigurable architecture via coarse-grained components and interconnects. This paper presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, DSP, FPGA, and coarse-grained reconfigurable architectures. RaPiD is a coarse-grained reconfigurable architecture specialized to the domain of signal and image processing. The RaPiD architecture provides a reconfigurable pipelined datapath controlled by efficient reconfigurable control logic: We have implemented the computationally intensive parts of an OFDM receiver on the RaPiD architecture and have developed careful estimates of corresponding implementations in representative ASIC, DSP and FPGA technology. Our results show that, for this application, RaPiD fills the cost/performance gap between programmable DSP and ASIC architectures, achieving a factor of 6 better than a DSP implementation but a factor of 6 less than an ASIC implementation.

Portable video supercomputing

As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing array, of portable products, the need for high efficiency, high throughput embedded processing will become an important challenge in computer architecture. Videocentric applications, such wireless videoconferencing, real-time video enhancement and analysis, and new, immersive modes of distance education, will exceed the computational capabilities of current microprocessor and digital signal processor (DSP) architectures. A new class of embedded computers, portable video supercomputers, will combine supercomputer performance with the energy efficiency required for deployment in portable systems. We examine one candidate portable video supercomputer, a low memory, monolithically integrated SIMD architecture (SIMPil) that exploits the substantial data parallelism that exists in a suite of implemented video processing applications. The processing element microarchitecture is optimized using a novel technique that combines application simulation and technology modeling to provide a desired combination of performance, area, and energy consumption. Analysis results show that, for MPEG encoding, a SIMPil array implemented in 100 nm CMOS provides 100x greater performance and 10x higher energy efficiency than today's DSPs implemented 150 nm CMOS. This is accomplished using execution parallelism and a carefully selected processing element design. This research demonstrates that appropriately designed SIMD arrays, implemented monolithically in today's technology, can provide high performance and high efficiency for embedded video processing.

XDSPCORE: a compiler-based configurable digital signal processor

XDSPCORE is a digital signal processor (DSP) architecture that enables time- and space-efficient execution of typical digital signal applications written in high-level languages. Our evaluation shows that the corresponding compiler can use all the DSP features as efficiently as a programmer coding in assembly language.

Classification of Power Quality Events Using Optimal Time-Frequency Representations—Part 2: Application

Classification of power-quality (PQ)-related voltage and current waveform disturbances is a key task for power system monitoring. A new method based on the optimized time-frequency representation (TFR) has been proposed in the first paper of this two-paper series. This paper (the second paper) presents a case study of PQ event classification with the proposed method. The classification algorithm has been successfully tested with 860 real world PQ events that cover five classes, achieving a recognition rate of 98%. The algorithm is implemented on a digital signal processor (DSP) based hardware system and optimized according to the DSP architecture to meet the hard real-time constraints. The DSP-based system is capable of processing a five-cycle (83.3 ms) PQ waveform within 11.2 ms. The real-time computing capability of the algorithm has been verified with this result. The scalability of this method is also discussed.

On Mapping Alogrithms to DSP Architectures

Our complex world is characterized by representation, transmission, and storage of information - and information is mostly processed in digital form. With the advent of DSPs (digital signal processors), engineers are able to implement complex algorithms with relative ease. Today we find DSPs all around us - in cars, digital cameras, MP3 and DVD players, modems, and so forth. Their widespread use and deployment in complex systems has triggered a revolution in DSP architectures, which in turn has enabled engineers to implement algorithms of ever-increasing complexity. A DSP programmer today must be proficient in not only digital signal processing but also computer architecture and software engineering.

A 1.1 G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.

Nanoscale Elastic-Property Mapping with Contact-Resonance-Frequency AFM

ABSTRACTWe describe a dynamic atomic force microscopy (AFM) method to map the nanoscale elastic properties of surfaces, thin films, and nanostructures. Our approach is based on atomic force acoustic microscopy (AFAM) techniques previously used for quantitative measurements of elastic properties at a fixed sample position. AFAM measurements determine the resonant frequencies of an AFM cantilever in contact mode to calculate the tip-sample contact stiffness k*. Local values for elastic properties such as the indentation modulus M can be determined from k* with the appropriate contact-mechanics models. To enable imaging at practical rates, we have developed a frequency-tracking circuit based on digital signal processor architecture to rapidly locate the contact-resonance frequencies at each image position. We present contact-resonance frequency images obtained using both flexural and torsional cantilever images as well as the corresponding vertical contact-stiffness (k*) image calculated from flexural frequency images. Methods to obtain elastic-modulus images of M from vertical contact-stiffness images are also discussed.

Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.

A virtual dsp architecture for audio applications from a complexity analysis of mpeg-4 structured audio

The MPEG-4 audio standard provides several toolsets for natural and synthetic sound coding. Among them, the most innovative in terms of multimedia applications is Structured Audio (SA), which implements a high level, structured description of sound instead of the usual compression techniques based on psychoacoustics and subband analysis. SA permits to encode synthesis and processing algorithms by its Structured Audio Orchestra Language (SAOL), and it can theoretically be used to specify any other audio decoder. This great flexibility introduces a challenging implementation problem, which in a normative framework has to be solved by a systematic approach. In the first part of the paper, it is described how the SA decoding process can be analyzed in a platform independent way in order to determine the fundamental figures of this coding technique; it is then shown how the proposed method is being used for the MPEG-4 SA conformance test. In the second part the design of a virtual digital signal processor (DSP) architecture is presented, based on the results of the complexity analysis. This architecture is able to exploit the intrinsic data level parallelism of many Audio algorithms and to consistently reduce the implementation cost. Experimental results prove the effectiveness of the approach and its suitability for implementations on modern superscalar DSPs and multimedia processors.

RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions

Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper, we present an algorithm to automatically generate RTs from a high-level processor description with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turnaround time in design space exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 very long instruction word digital signal processor and DLX processor architectures, and a suite of multimedia and scientific applications.

DSP architectures

As far as the future of communication is concerned, we have seen that there is great demand for audio and video data to complement text. Digital signal processing (DSP) is the science that enables traditionally analog audio and video signals to be processed digitally for transmission, storage, reproduction and manipulation. In this paper, we will explain the various DSP architectures and its silicon implementation. We will also discuss the state-of-the art and examine the issues pertaining to performance.

A high-performance communication service for parallel computing on distributed DSP systems

Rapid increases in the complexity of algorithms for real-time signal processing applications have led to performance requirements exceeding the capabilities of conventional digital signal processor (DSP) architectures. Many applications, such as autonomous sonar arrays, are distributed in nature and amenable to parallel computing on embedded systems constructed from multiple DSPs networked together. However, to realize the full potential of such applications, a lightweight service for message-passing communication and parallel process coordination is needed that is able to provide high throughput and low latency while minimizing processor and memory utilization. This paper presents the design and analysis of such a service, based on the message passing interface specification, for unicast and collective communications.

Lattice codebook enumeration for generalized Gaussian source

The goal of this correspondence is to propose a low-complexity enumeration algorithm for lattice vectors, based on a geometrical interpretation and valid for different source distributions, i.e., for different L/sub p/-norms in the range 0<p/spl les/2. As a particular case, we obtain the Laplacian enumeration formula of Fischer. This point of view offers various advantages and particularly it enables one to make the link with the generalized theta-series and to reduce the algorithm to the calculation of a few convolutional products in the special cases p=1 and p=2. Using a dedicated digital signal processing (DSP) architecture, convolutional products are easy to implement and require few arithmetic operations. Our algorithm, developed for the Z/sup n/ lattice, can be generalized to other lattices like the D/sub n/.

Performance evaluation and optimal design for FPGA-based digit-serial DSP functions

As field programmable gate array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. Digit-serial DSP architectures have been effective implementation method for FPGAs. In this work, a method of implementing digit-serial DSP architectures on FPGAs is presented, and their performance is evaluated with the objective of finding and developing the most efficient digit-serial DSP architectures on FPGAs. This paper discusses area costs and operational delays of the various digit-serial DSP functions and presents the area/delay models on Xilinx XC4000-series FPGAs. These area/delay models can make predictions of performance and hardware resource utilization before a lengthy layout and synthesis process is undertaken. The results show that the area/delay models proposed here are valid and the digit-serial DSP designs are promising candidates for efficient FPGA implementations.

A DSP Architecture for High‐Speed FFT in OFDM Systems

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 µm standard cell library, and then verified the functions thoroughly.

The Equator MAP-CA/spl trade/ DSP: an end-to-end broadband signal processor/spl trade/ VLIW

Today's multimedia services, both at the server/headend and the client/consumer end, require high computational performance to support video encoding, decoding, and transcoding. Traditionally, the processing requirements have been met by application-specific processors (ASIC). What once were standalone single-function devices are now network-connected, multifunction service platforms - the Internet-ready digital television/video recorder/teleconference/game platform, for example. As a result, these platforms now must support multiple image formats, compression standards, and processing algorithms. Equator Technologies has developed a high-performance, programmable system on a chip, the MAP-CA digital signal processor (DSP), to address this requirement. The MAP-CA DSP combines general-purpose reduced instruction set computer processing with high-performance image and signal processing in a very long instruction word framework. The chip is designed to replace hardwired ASIC in a variety of products, including digital head-end, networking products, and consumer applications. We present an analysis of the MAP-CA DSP architecture and provide several performance benchmarks with popular media processing applications.