Introduction to the Special Issue on SAMOS 2007

Abstract

This special issue includes a selection of the best papers from the 2007 SAMOS VII Symposium. The International Symposium on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS) is an event which annually takes place on the scenic Mediterranean island of Samos. It comprises two co-located events—the International SAMOS Conference and the SAMOS Workshop. In 2007 more than 200 papers were submitted for these two events. After a very competitive selection process only about 30% of these papers have been selected for presentation. According to the Symposium’s ranked results and the results of a second stage review process of all presentations from SAMOS, the following eight papers related to architectures and implementations of embedded systems have been selected for publication in this special issue. We would like to thank all reviewers of the SAMOS Workshop and particularly all reviewers of this special issue for their detailed and intensive review work. The investment of their time and insight is very much appreciated and helped to generate this selection of high quality technical papers. The important field of Digital Signal Processor Architectures which is classically one of the focus topics of SAMOS is covered in this special issue by three papers: Thuresson et al. present a paper which is entitled “FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.” Within this paper the authors present a highly efficient DSP architecture and discuss specific elements of this architecture including fine-grained control and a flexible interconnect which lead to significant speedups and significant energy savings. They elaborated on their flexible interconnect that allows the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore provides specialized datapath units to be inserted and utilized within the same architecture and compilation framework. The problem of memory bottlenecks in modern DSP architectures is addressed by the paper of Pitkaenen et al. which is entitled “Parallel Memory Architecture for Application-Specific Instruction-Set Processors.” In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed parallel memory system is attached to an ASIP core and comparisons on area, power, and critical path are presented. Significant power savings can be obtained by exploiting their parallel memory system instead of multi-port memories. Memory access problems are also addressed in the paper of Galuzzi et al. In “High-bandwidth Address Generation Unit” they present an efficient data fetch circuit to retrieve several operands from an n-way interleaved memory system in a single machine cycle. The proposed address generation unit operates with an improved version of a low-order interleaved memory access approach. The presented design supports data structures of arbitrary lengths and various odd strides. J Sign Process Syst (2009) 57:1–3 DOI 10.1007/s11265-008-0220-8