Architectural Enhancements Research Articles

Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces

Programmable logic cores (PLCs) offer a means of providing post-fabrication reconfigurability to a SoC design. This ability has the potential to significantly enhance the SoC design process by enabling post-silicon debugging, design error correction and post-fabrication feature enhancement. However, circuits implemented in general purpose programmable logic will inevitably have lower timing performance than fixed function circuits. This fundamental mismatch makes it difficult to use the PLC effectively. We address this problem by proposing changes to the structure of the PLC itself; these architectural enhancements enable circuit implementations with high performance interfaces. In previous work we addressed system bus interfaces, in this work we address direct synchronous interfaces. Our results show significant improvement in PLC interface timing, such that interaction with full-speed fixed-function SoC logic is possible. Our enhanced PLCs are able to implement direct synchronous interfaces running at, on average, 662 MHz (compared to 249 MHz in regular programmable logic). We are able to do this without compromising the basic structure or routiblity of the programmable fabric. At the same time, we show that the area overhead for these architectural changes was approximately 1%.

WebSphere Portal 6.1

IBM’s Portal technology continues to evolve as a powerful infrastructure for integrating the IT landscape, by presenting it as a consolidated view to the user community. The new capabilities of WebSphere Portal 6.1 are the outcome of a world-wide development team, which focused on this release for the past 2 years. During that time major architectural enhancements have been introduced and a significant amount of code was written. In this article the authors will describe how developers and testers have adopted agile principles to collaborate across the globe. In detail, aspects like an iterative approach, test driven development, budget based prioritization and cross-organization teaming will be discussed. The authors will also cover how “tiger teams” interact with customers by making early code drops available and responding to feedback.

Architecting phase change memory as a scalable dram alternative

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance. We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures

Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia and biomedical applications. The instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy consumption and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and supports the execution of multiple incompatible loops in parallel in a uni-processor system. We present different methods to implement the loop controller architecture, compare them, and show that distributing the instruction memory helps to reduce the interconnect cost as well. This architecture enhancement can reduce the energy consumed in the instruction memory hierarchy by 59% and improve the performance by 22% compared to hardware based enhanced SMT based architectures.

Architectural sound enhancement with pre-filtered masking sound

A unique, fully integrated, fully programmable, and highly flexible sound distribution system and methodology for providing masking sound, background music, and paging capabilities in up to eight zones of a building or space is provided. The methodology embodied in the system includes internal masking sounds that are uniquely pre-filtered to provide efficient and effective masking of distracting sounds within selectable zones of the space with a minimum masking sound dB sound level and with a pleasant sounding and non-annoying masking sound. The system also incorporates the capacity to be controlled from a remote or local telephone to adjust the volume level in any zone serviced by the system by issuing appropriate DTMF codes from the telephone's keypad. Unique bi-tone diagnostic functions are provided for assuring that the entire system is correctly wired and installed and for troubleshooting operational anomalies. ⅓ octave equalization is provided to compensate for known frequency response characteristics of the flat panel radiators of the system and to compensate for varying room acoustics to provide a low special variation of sound among the various zones of the space. The result is a high quality high fidelity sound that is consistent from zone to zone.

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography

This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F 2 163 and F 2 193, for application in a high-performance embedded system implementing elliptic curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a coprocessor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software co-design approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results shows that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor-based hardware.

Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA

Increasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a software defined radio application that serves as a vehicle for investigating effective communication between the PowerPC405 processor and the surrounding FPGA fabric.

PRISM: A Video Coding Paradigm With Motion Estimation at the Decoder

We describe PRISM, a video coding paradigm based on the principles of lossy distributed compression (also called source coding with side information or Wyner-Ziv coding) from multiuser information theory. PRISM represents a major departure from conventional video coding architectures (e.g., the MPEGx, H.26x families) that are based on motion-compensated predictive coding, with the goal of addressing some of their architectural limitations. PRISM allows for two key architectural enhancements: (1) inbuilt robustness to "drift" between encoder and decoder and (2) the feasibility of a flexible distribution of computational complexity between encoder and decoder. Specifically, PRISM enables transfer of the computationally expensive video encoder motion-search module to the video decoder. Based on this capability, we consider an instance of PRISM corresponding to a near reversal in codec complexities with respect to today's codecs (leading to a novel light encoder and heavy decoder paradigm), in this paper. We present encouraging preliminary results on real-world video sequences, particularly in the realm of transmission losses, where PRISM exhibits the characteristic of rapid recovery, in contrast to contemporary codecs. This renders PRISM as an attractive candidate for wireless video applications.

Exploring opportunities to improve the performance of a reconfigurable instruction set processor

In this paper, at a reconfigurable instruction set processor (RISP) is targeted, which tightly couples a coarse-grain reconfigurable functional unit (RFU) to a RISC processor. Furthermore, the architecture is supported by a flexible development framework. By allowing the definition of alternate architectural parameters, the framework can be used to explore the design space and fine-tune the architecture at design time. Initially, two architectural enhancements, namely partial predicated execution and virtual opcode are proposed and the extensions performed in the architecture and the framework to support them, are presented. To evaluate these issues, kernels from the multimedia domain are considered and an exploration to derive an appropriate instance of the architecture is performed. The efficiency of the derived instance and the proposed enhancements are evaluated using an MPEG-2 encoder application.

Enforcing provisioning and authorization policy in the Antigone system

Prior works in communication security policy have focused on general-purpose policy languages and evaluation algorithms. However, because the supporting frameworks often defer enforcement, the correctness of a realization of these policies in software is limited by the quality of domain-specific implementations. This paper introduces the Antigone communication security policy enforcement framework. The Antigone framework fills the gap between representations and enforcement by implementing and integrating the diverse security services needed by policy. Policy is enforced by the run-time composition, configuration, and regulation of security services. We present the Antigone architecture, and demonstrate non-trivial applications and policies. A profile of policy enforcement performance is developed, and key architectural enhancements identified. We also consider the advantages and disadvantages of alternative software architectures appropriate for policy enforcement.

Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography

Digit serial multipliers are used extensively in hardware implementations of elliptic and hyperelliptic curve cryptography. This contribution shows different architectural enhancements in least significant digit (LSD) multiplier for binary fields GF(2m). We propose two different architectures, the double accumulator multiplier (DAM) and N-accumulator multiplier (NAM), which are both faster compared to traditional LSD multipliers. Our evaluation of the multipliers for different digit sizes gives optimum choices and shows that currently used digit sizes are the worst possible choices. Hence, one of the most important results of this contribution is that digit sizes of the form 2l - 1, where l is an integer, are preferable for the digit multipliers. Furthermore, one should always use the NAM architecture to get the best timings. Considering the time area product DAM or NAM gives the best performance depending on the digit size

Architectural enhancements for network congestion control applications

Complex network protocols and various network services require significant processing capability for modern network applications. One of the important features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications-scheduling and queue management algorithms, and we propose application-specific acceleration techniques that use instruction-level parallelism (ILP) and packet-level parallelism (PLP) in these applications. From the PLP perspective, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, a large number of processing elements (PEs) and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. A 32-PE enhancement yields 24times speedup for weighted fair queueing (WFQ) and 27times speedup for random early detection (RED). For ILP, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10%-12% improvement in performance for instruction set enhancements. As the performance of general-purpose processors rapidly increases, defining architectural extensions (e.g., multi-media extensions (MMX) as in multimedia applications) for general-purpose processors could be an alternative solution for a wide range of network applications

Consuming colonial nostalgia: The monumentalisation of historic hotels in urban South-East Asia

: This article examines the renovation and commercial re-launch in the 1990s of some of the grand hotels built in South-East Asia during the high colonial era (1880s–1910s) and their social construction as historic monuments. The analysis focuses on architectural enhancement and discursive authentication as the key practices whereby the semblance of historic authenticity is bestowed on these hotels and made available as nostalgia to consumers. The article also considers whether renovated colonial hotels should be regarded as sites of consumption or as emerging ‘mnemonic sites’, filling in the vacuum caused by the progressive obliteration of ‘mnemonic environments’ in South-East Asia's urban landscape.

The irregular Z-buffer

The classical Z-buffer visibility algorithm samples a scene at regularly spaced points on an image plane. Previously, we introduced an extension of this algorithm called theirregular Z-bufferthat permits sampling of the scene from arbitrary points on the image plane. These sample points are stored in a two-dimensional spatial data structure. Here we present a set of architectural enhancements to the classical Z-buffer acceleration hardware which supports efficient execution of the irregular Z-buffer. These enhancements enable efficient parallel construction and query of certain irregular data structures, including the grid of linked lists used by our algorithm. The enhancements include flexible atomic read-modify-write units located near the memory controller, an internal routing network between these units and the fragment processors, and a MIMD fragment processor design. We simulate the performance of this new architecture and demonstrate that it can be used to render high-quality shadows in geometrically complex scenes at interactive frame rates. We also discuss other uses of the irregular Z-buffer algorithm and the implications of our architectural changes in the design of chip-multiprocessors.

QoS control schemes for two-stage Ethernet passive optical access networks

Ethernet passive optical networks (EPONs) have emerged as the one of the most promising candidates for next-generation access networks. These new architectures couple low-cost optics with advanced edge electronics to offer vastly improved scalability over competing digital subscriber line and cable modem offerings. This paper proposes several novel architectural enhancements for EPON, which will help increase the viability of optical access over a broader range of subscriber access scenarios. Specifically, this paper proposes a two-stage EPON architecture that allows more end-users to share an optical line terminal link, and enables longer access reach/distances (beyond the usual 25 km distance). In addition, a new dynamic bandwidth allocation (DBA) algorithm is proposed to effectively allocate bandwidths between end users. This DBA algorithm can support differentiated services in a network with heterogeneous traffic. We conduct detailed simulation experiments to study the performance and validate the effectiveness of the proposed architecture and algorithms.

Protecting cryptographic keys and computations via virtual secure coprocessing

Cryptographic processing is a critical component of secure networked computing systems. The protection offered by cryptographic processing, however, greatly depends on the methods employed to manage, store, and exercise a user's cryptographic keys. In general, software-only key management schemes contain numerous security weaknesses. Thus, many systems protect keys with distributed protocols or supplementary hardware devices, such as smart cards and cryptographic coprocessors. However, these key protection mechanisms suffer from combinations of user inconvenience, inflexibility, performance penalties, and high cost.In this paper, we propose architectural enhancements for general-purpose processors that protect core secrets by facilitating virtual secure coprocessing (VSCoP). We describe modest hardware modifications and a trusted software library that allow common computing devices to perform flexible, high-performance, and protected cryptographic computation. The hardware additions include a small key store in the processor, encryption engines at the cache-memory interface, a few new instructions, and minor hardware platform modifications. With these enhancements, users can store, transport, and employ their secret keys to safely complete cryptographic operations in the presence of insecure software. In addition, we provide a foundation with which users can more securely access their secret keys on any Internet-connected computing device (that supports VSCoP) without requiring auxiliary hardware such as smart cards.

Network architecture and medium access control for deploying third generation (3G) wireless systems over CATV networks

We propose a novel and cost-effective approach for the deployment of third generation (3G) wireless systems over hybrid fiber coaxial (HFC) CATV networks. The main goal is to facilitate 3G deployment over the existing CATV plant and reduce the large cost required for building a dedicated last mile infrastructure for 3G access networks. Our proposal reduces the last mile cost by sharing the existing CATV network and using the standard equipment and protocols of data-over-cable systems interface specifications (DOCSIS). This allows rapid deployment of 3G wireless systems, facilitates convergence of wireless and wireline networks and paves the way towards all IP wireless networks. Enhancements to the DOCSIS medium access control (MAC) protocol must be implemented in order to support Quality of Service (QoS) guarantees for 3G data and signaling traffic. This paper presents the proposed 3G over CATV network architecture and DOCSIS medium access control (MAC) enhancements for enabling the support of QoS guarantees for 3G data and signaling traffic. The proposed MAC enhancements can reduce the access delay for delay-sensitive traffic by 30 to 40% over existing DOCSIS MAC without compromising QoS guarantees for other traffic classes, or the DOCSIS channel utilization. Copyright © 2004 John Wiley & Sons, Ltd.

LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between the different architectures including our enhancements and others is presented using simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.

B03: High speed arithmetic calculation unit for Xilinx type FPGAs

The paper presents new approach to design and implementation of an arithmetic calculation unit within FPGA devices. The unit is purposefully designed and takes advantage of specific architectural enhancements. Optimal implementation result and high speed of operation is achieved by direct event driven architecture that allows to branch the process to several different calculation depending on external events This unit offers easy modification of arithmetic formulas either statically or in a runtime.

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Network-on-a-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance system-on-chip architectures in the nanoscale regime. Many real-time applications require input data that arrives with low delay jitter. Such communication traffic can only be supported by incorporating multiple levels of service in the interconnection network. Further, as technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, and radiation induced effects, that are likely to reduce the reliability of data. Hence, effective error control schemes are required for ensuring data integrity. This paper addresses two important aspects of NoC architectures, quality of service and error control schemes and makes the following contributions: (i) it presents techniques for supporting guaranteed throughput (for low delay jitter traffic) and best-effort traffic quality levels in NoC router, (ii) it presents architectures for integrating error control schemes in the NoC router architecture, and (iii) it presents cycle accurate power and performance models of the two architecture enhancements for a mesh based NoC architecture.