Approximate Multipliers Research Articles

Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing

The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.

On the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers

With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.

Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications

The imprecise multipliers are the building blocks of error-tolerated applications such as image processing. This article introduces area-efficient n×n approximation multipliers using a proposed 3-bit decoder logic algorithm. The theme of the work is to minimize the partial product rows effectively using the proposed algorithm, thereby simplifying the accumulation stage process. As a result, the suggested N×N imprecise multipliers reduce the design complexity. The suggested and existing circuits in the literature are simulated using the Cadence RTL compiler with TSMC 180 nm technology. Implementation outcomes indicate that the suggested 8 × 8 and one of the proposed 16 × 16 approximate multipliers achieve 46.70%, 45.96%, and 46.58%, 28.11% area and power reductions compared to the accurate multipliers. Compared with the exact multiplier, the suggested 8 × 8 approximate model reduces the Area-Delay Product (ADP) and Area-Delay-Power Product (ADPP) by 49.95% and 72.95%, respectively, with reasonable error metrics. Also, the proposed 16 × 16 approximate multipliers maintain a better performance balance between area demand and allowable error rate. Moreover, while extending in image multiplication, smoothing and sharpening, the 8 × 8 proposed approximate multiplier attains an acceptable mean structural similarity index value with less area requirement than previous approximate multiplier designs.

Efficient and low-cost approximate multipliers for image processing applications

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works.

New design for error-resilient approximate multipliers used in image processing in CNTFET technology

New design for error-resilient approximate multipliers used in image processing in CNTFET technology

Implementation of a Robust Framework for Low Power Approximate Multiplier Using Novel 3:2 and 4:2 Compressor for Image Processing Applications

Background: The technique of approximation allows for a trade-off between accuracy, speed, area use, and power usage. It is essential in applications that can withstand errors because even a modest accuracy loss can have a significant impact on the result. Methods: In this research, a novel approximate adder and exact 3:2 and 4:2 compressors are used to create a power-efficient approximation multiplier. In order to reduce the partial product while keeping a fair level of accuracy, approximate compressors are used. Results: The proposed approximate multiplier performs better in terms of LUTs, area, memory usage, and power consumption when compared to state-of-the-art work. Conclusion: The proposed approximate multiplier is applied to two sets of images for image blending to validate the results. PSNR values of 25.49 dB and 24.7 dB were attained for set 1 and set 2, respectively.

Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximate multiplier design, proposed Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier using 15–4 Approximate Compressors (hybam-AC) is used for decreasing power consumption and design complexity. The simulation of the proposed model is implemented in Verilog and the design is synthesized in FPGA utilizing Xilinx ISE 14.5. The proposed DA-AFIR-leadx-hybam-AC filter design attains 33.6%, 22.75%, 29.69% lower power and 43.58%, 11.3%, 33.07% lower delay than the existing approaches, like DA-AFIR-MLDA-RNS, DA-AFIR-Hyb-CSD-ABR, DA-AFIR-SOPOT-MPGBP. Finally, the proposed DA-AFIR-leadx-hybam-AC filter design is applied for noise removal application in sensor nodes. The proposed Filter is implemented in MATLAB/Simulink for reading input signal.

Design of Energy-Efficient RFET-Based Exact and Approximate 4:2 Compressors and Multipliers

The ever-increasing demand for low-power and area-efficient circuits for use in battery-powered devices and the CMOS scaling problems have attracted the attention of VLSI designers to beyond-CMOS technologies like Reconfigurable Field-Effect Transistors (RFETs). Improving the efficiency of multipliers is critical as the core component of many applications such as image processing and Machine Learning (ML). This paper proposes a compact and energy-efficient RFET-based architecture for the 4:2 compressor and Dadda multiplier, leveraging transistor-level reconfigurability and multi-input support of the RFET. Moreover, we propose a novel approximate 4:2 compressor based on efficient RFET logic cells to cater to the needs of error-resilient applications. Extensive circuit-level simulations with 14nm germanium nanowire (GeNW) RFET technology show that the proposed RFET-based exact multiplier improves the power consumption and power-delay product (PDP) by 65% and 45%, respectively, compared to the conventional CMOS-based counterpart in 14nm FinFET technology. Besides, we show that utilizing the proposed approximate compressor, the area and PDP of the multiplier reduce by 46% and 42%. The effectiveness of the approximate multiplier is evaluated in the image multiplication, and the average PSNR and SSIM values are 31.39 and 0.87, respectively.

CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications

CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications

Design and realization of area-efficient approximate multiplier structures for image processing applications

The multiplier is a vital element in real-time applications. This work intends to build area-efficient multipliers based on the approximation concept. The approximate computing scheme receives considerable attention generally in error-resilient applications like image processing which reduce the design parameters at the expense of slightly sacrificing the precision of the performance. This paper proposes the two approximate multipliers (PAM-1 & PAM-2) using the modified 4:2 compressor, full-adder, and sum generation component. The main essence of the proposed approximate multiplier structures is to divide the partial product generation rows into (n/2) stages. The proposed approximate compressors are employed to compress partial products on the LSB side of the multiplier, while accurate compressors are utilized on the MSB side. By effectively combining approximate and exact compressors, the developed approximate multipliers achieve better results in terms of circuit parameters and acceptable error metrics compared to existing imprecise designs. These improvements are reflected in the implementation tables reported in the paper. Compared with the accurate multiplier, the proposed multiplier (PAM-2) reduce the area requirement, delay and power consumption by 38%, 46%, and 50%, respectively. In addition, while extending to image processing applications like multiplication, smoothing, and sharpening, the proposed approximate multipliers attain a better image quality than existing designs, which measure in terms of the mean structural similarity index metric.

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing

This paper presents the Weight-aware Approximate Multiplication Architecture (W-AMA) for Deep Neural Networks (DNNs). Considering the Gaussian-like weight distribution, it deploys an accuracy-configurable computing component to improve the computational efficiency. Two techniques for effectively integrating the W-AMA into DNN accelerator are presented: (1) A Cartesian Genetic Programming (CGP) based approximate multiplier is designed and selectable to compute the Least Significant Bit (LSB) for a higher accuracy mode. The Reward–Penalty-Coefficient (RPC) is proposed to achieve the internal-compensation. (2) The Hessian-Aware-Approximation (HAA) method is utilized for hybrid approximate modes cross-layer mapping. Based on the W-AMA, an energy-efficient DNN accelerator is proposed and evaluated on 28 nm technology. It can achieve the energy efficiency of 9.6 TOPS/W, and the computational energy efficiency can be improved by 1.5× compared with the standard units, with an 0.52% accuracy loss on CIFAR-10 using ResNet-18.

A High-Accuracy Low-Power Approximate Multipliers with New Error Compensation Technique for DSP Applications

A High-Accuracy Low-Power Approximate Multipliers with New Error Compensation Technique for DSP Applications

A Design and Investigation Inexact Compressor Based on Low Power Multiplier

To achieve low power consumption and high performance, an approximate multiplier is a commonly used operation. A new approximate computation method has been used for Error Tolerant Image Processing applications. This operation is popular in error tolerance applications. Inexact computing is applied to error-tolerant digital signal processing applications where error can be tolerated. Multiplier is the basic unit of arithmetic logic unit of any computer computational unit. In this paper, a new approximate compressor computation method is proposed for error-tolerant image processing applications. An approximate compressor has been designed for better output power with an improved figure of merit. A comparison of the proposed compressor with the previous 4:2 compressor design has been investigated and a reduction in area, delay and power consumption has been achieved. A similar algorithm has been applied to 8-bit multiplier applications which have considerable error performance. With the newly designed multiplier using a compressor, the simulation results compared the best power utilization. The results of designing the multiplier indicate that the proposed design of a multiplier using an approximate compressor achieves a reduction in power by 129[Formula: see text]mw.

Improved approximate multiplier architecture for image processing and neural network applications

This paper proposes new approximate unsigned multiplier architecture which aims to reduce the power consumption and area with better accuracy. In our proposed design, the approximation is applied in partial product generation (PPG) and partial product reduction (PPR) stages. In PPG, we proposed two approximate sub-multipliers to reduce the number of partial product rows. For the 8-bit multiplier design, experimental results show an improvement of 38.78% and 50.53% in power and power-delay-product respectively, when the proposed design is compared against the exact design, and 26.11% and 33.17% respectively when compared to existing Ax8-1 design, without compromising on the accuracy. Finally, proposed designs are validated using image processing and neural network applications.

Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs

Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5%–42.9%), Power Delay Product (PDP saving 49.4%–53%), performance metric (LUTs × critical path delay (CPD) × PDP saving 68.9%–73.1%) and errors (70% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators.

A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier

For Convolutional Neural Networks (CNNs), Depthwise Separable CNN (DSCNN) is the preferred architecture for Application Specific Integrated Circuit (ASIC) implementation on edge devices. It benefits from a multi-mode approximate multiplier proposed in this work. The proposed approximate multiplier uses two 4-bit multiplication operations to implement a 12-bit multiplication operation by reusing the same multiplier array. With this approximate multiplier, sequential multiplication operations are pipelined in a modified DSCNN to fully utilize the Processing Element (PE) array in the convolutional layer. Two versions of Approximate-DSCNN (A-DSCNN) accelerators were implemented on TSMC 40 nm CMOS process with a supply voltage of 0.9 V. At a clock frequency of 200 MHz, the designs achieve 4.78 GOPs/mW and 4.89 GOP/mW power efficiency while occupying 1.16 mm2 and 0.398 mm2 area, respectively.

Designing of Energy-Efficient Approximate Multiplier Circuit for Processing Unit of IoT Devices

Designing of Energy-Efficient Approximate Multiplier Circuit for Processing Unit of IoT Devices

Design methodology for highly accurate approximate multipliers for error resilient applications

Approximate computing has become the paradigm shift for applications such as neural networks and image processing, where accurate computation is not needed and intends to improve area, power, and speed. New Multiplier architectures are proposed in this paper based on an algorithm which assigns the appropriate approximate compressor adaptively from existing set of compressors to improve the accuracy in the corresponding partial product column. Experimental results prove that the existing unsigned multiplier architectures have less accuracy than the proposed designs. To quantify the performance of the proposed designs they were assessed using image processing and neural network applications. From the results, it can be deduced that the proposed architectures achieve up to 43% increase in PSNR when compared to the existing designs, with up to 14.3% increase in power consumption.

Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption

Many modern compute-intensive applications require arithmetic results (usually multiplication) to be represented as analog signals. Using digital multipliers followed by digital-to-analog conversion (DAC) results in high energy and performance costs. This is because digital multipliers have costly carry propagation, and DAC circuits add associated conversion costs. Another concern, especially for arithmetic on the edge, is the need for nonvolatile operands in the face of power uncertainty. To deal with this, nonvolatile memory technologies have been combined with in-memory computing. This paper proposes a mixed-signal multiplier which directly generates an analog product based on two digital input operands. Fundamental to the design are transistor-memristor cells, organized in a crossbar structure. Using analog resistive partial product accumulation in the crossbar, the approximate multiplier eliminates the need for carry propagation and an explicit DAC. It also provides asymmetric nonvolatility making memristor writing a rare event, extending the application significance of the method. The design is shown to be functionally correct up to 4-bit, and achieves 8× to over 300× speedup, competitive peak-power and orders of magnitude energy reduction, compared with existing full-digital memristor-based multipliers and low-power multiplication DAC solutions.

AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch

Current state-of-the-art employs approximate multipliers to address the highly increased power demands of DNN accelerators. However, evaluating the accuracy of approximate DNNs is cumbersome due to the lack of adequate support for approximate arithmetic in DNN frameworks. We address this inefficiency by presenting AdaPT, a fast emulation framework that extends PyTorch to support approximate inference as well as approximation-aware retraining. AdaPT can be seamlessly deployed and is compatible with the most DNNs. We evaluate the framework on several DNN models and application fields including CNNs, LSTMs, and GANs for a number of approximate multipliers with distinct bitwidth values. The results show substantial error recovery from approximate re-training and reduced inference time up to 53.9x with respect to the baseline approximate implementation.