Digital Signal Processing Applications Research Articles

An optimization framework for dynamic pipeline management in computing systems

Dynamic computer pipelines use feedback loops for iterative computation, due to which, data items, while traversing them often collide with one another. These pipelines, therefore, employ specialized mechanisms to detect and avoid such collisions in real-time. Mostly, this is done by deciding when, and when not, to allow newer data items to enter the pipeline. We will show that such decisions may lead to different throughput, and guaranteeing optimal performance is an optimization problem. We begin by building a mathematical model of dynamic pipelines, and make use of genetic algorithm to yield near-optimal throughput. The proposed optimization technique accounts for the hardware overhead, incurred due to the extensions in the pipeline organization, as suggested by itself. Our confidence in the results stems from simulation of 10,000 dynamic pipeline organizations, and for verification of results, we present hardware implementation of one of those. The proposed framework will specifically be useful in embedded systems for digital signal processing applications.

Matched Filter Based Detection over Time Varying Fading Channels with Reduced Complexity

Challenges in high speed data transmission technology over time varying fading channels is addressed in this paper. More precisely, the signal processing at the receiver side has to be analyzed for such systems, as it is well known that the mobile radio channels are characterized by frequency selective fast fading is typically introduced error in the received signal. Thus, the performance of the receiver severely degraded because of such factors. Specifically, this paper deals with the detection using a matched filter followed by low weight near maximum likelihood detector (NMLD) for the application of digital signal processing in outdoor vehicular radio environments. Nearly Maximum Likelihood Detection depends on the length of the stored vectors as well as depends on the numbers of the stored vector. In [1] complexity is reduced by reducing the stored vectors, in this paper same NMLD used but the complexity of the matched filter is reduced by some variance. Finally, the bit error rate (BER) is measured with signal to noise ratio.

DSP Technology and Its Application in Fuze Signal Processing

The continuous innovation of the embedded digital signal processor (DSP) brings new opportunities for the breakthrough of fuze technology, so that the weapon system can complete the detection battlefield, precise control, high-efficiency damage without changing the existing shape and volume of the fuze. This paper first introduces the advantages and characteristics of DSP chips, then summarizes the application of DSP in a variety of fuze signal processing. Finally, the development direction and application trend of DSP in fuze are prospected.

ВІДТВОРЕННЯ СИГНАЛІВ ТА ЗОБРАЖЕНЬ ЗА БІСПЕКТРОМ У ПРИСУТНОСТІ ШУМІВ

In a number of practical applications of digital signal processing, the process under study may include correlated spectral components or phase coupling. Extracting the phase relationships provides very important and useful information for the correct understanding, analysis, and description of the properties of physical phenomena generating these processes. However, such information is irretrievably lost when using classical methods of signal processing using energy statistics, i.e. second-order statistics. Obtaining estimates of signal parameters and analyzing them using third-order correlation functions and bispectrum makes it possible to learn much more about signal properties than when using conventional correlation functions. Estimating the bispectral density (third order spectral density), in contrast to estimating the energy spectrum, makes it possible not only to describe the characteristics of the observed process correctly, but also to preserve and, if necessary, extract the phase characteristics of the component, which includes the observed process. Therefore, in a number of applied tasks of telecommunications, as well as tasks of image processing and other bisection analysis, often serves as an effective tool of signal processing. The aim of the article is to study the feasibility of using a recursive algorithm when restoring a waveform and image by bispectrum in the noise environment. The following types of signals were selected for the study: rectangular, triangular, Gaussian impulses and signal-triplet. They were distorted with additive white Gaussian noise Test image was distorted by additive white Gaussian, pulsed, Poisson and multiplicative noises. Analysis of the signal recovery results indicates that as the noise power increases, the quality of the recovery decreases. The effect of random signal shift does not affect the shape of the recovered signal. Analysis of the image recovery results indicates image recovery, but this algorithm introduces distortions in the form of an offset

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

Progressive Failure Monitoring of Fiber-Reinforced Metal Laminate Composites Using a Nondestructive Approach

Fiber-reinforced metal laminate (FRML) composites are currently used as a structural material in the aerospace industry. A common FRML, glass layered aluminum reinforced epoxy (Glare), possesses a set of mechanical properties which was achieved by designing its layup structure to combine metal alloy and fiber-reinforced polymer phases. Beyond static and dynamic mechanical properties at the material characterization phase, however, the need exists to develop methods that could assess the evolving material state of Glare, especially in a progressive failure context. This paper presents a nondestructive approach to monitor the damage at the material scale and combine such information with characterization and postmortem evaluation methods, as well as data postprocessing to provide an assessment of the failure process during monotonic loading conditions. The approach is based on multiscale sensing using the acoustic emission (AE) method, which was augmented in this paper in two ways. First, by applying it to all material components separately in addition to actual Glare specimens. Second, by performing testing and evaluation at both the laboratory scale as well as at the scale defined inside the scanning electron microscopy. Such elaborate testing and nondestructive evaluation results provided the basis for the application of digital signal processing and machine learning methods which were capable to identify data trends that are shown to be correlated with the evolution of failure modes in Glare.

Cardinal MK-spline signal processing: Spatial interpolation and frequency domain filtering

Altering the sampling rate of a digital signal by interpolation is a very important task in many digital signal processing applications. MK-spline is a kind of promising cardinal spline or explicit interpolation spline, which can achieve the purpose of interpolation without solving systems of coefficient equations, and which can inherit almost all good properties of B-splines, such as local support, high order smoothness, and central symmetry. For using MK-spline as a tool in signal and image processing, we first provide elementary theory which is composed of MK-spline convolution representation, related Fourier transform in continuous domain, and z transform of expanded MK-spline in discrete domain. Then, a cubic MK-spline interpolating filter (MKIF) is designed as a physically realizable FIR digital filter based on the discrete convolution operation which outputs directly a discrete smoothed signal from an input discrete signal. Next, frequency domain MK-spline lowpass and highpass filters are also devised in this study for image smoothing, sharpening, and denoising. Finally, simulated experiments are presented in different dimensional data formats in order to verify that the convolution-based MKIF is faster than those based on traditional continuous method, and that the proposed MK-spline filters have significantly good characteristics in the processes of signal reconstruction, image enlargement, and image denoising, when compared with traditional linear filters and classical B-spline filters.

Early Output Quasi-Delay-Insensitive Array Multipliers

Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.

VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes

Residue number system (RNS) in computer arithmetic is an efficient parallel computation number system that employs forward conversion, residue arithmetic based arithmetic manipulation and reverses conversion, which all together increases the speed of computation in various digital signal processing applications. Nevertheless power requirement for the wireless sensor node is more important, hence this work focuses on the design and implementation of power efficient RNS based digital signal processor architecture using folded tree based parallel prefix adder by employing Chinese Remainder Theorem—I.

Optimized implementation of digital signal processing applications with gapless data acquisition

This paper presents novel models and design optimization methods for gapless deep waveform applications, where continuous streams of data must be processed reliably without dropping any samples. The approaches developed in this paper involve unified dataflow-based modeling of the interfaces and signal processing functionality of gapless deep waveform analysis. Bottleneck actors (computational modules) in the resulting dataflow model are then identified and tackled with approximate computing techniques. These techniques are developed and configured carefully so that large performance gains are achieved while keeping reductions in signal processing accuracy to a manageable level. Efficient actor- and graph-level code optimization techniques are also applied to further improve real-time performance. In addition to providing accurate, real-time processing on the experimental platform used in our experiments, the algorithm- and model-based formulation of the contributions in this part promotes their general utility in deep waveform analysis and their retargetability to other platforms.

Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. But the scaling of in-place RFFT architecture for higher lengths and higher throughput is a challenging issue due to increasing memory access conflict and higher memory bandwidth requirement. In this paper, a design approach is presented to develop an area-delay and energy-efficient architecture for in-place RFFT. Generally, an in-place fast Fourier transform (FFT) structure consists of a butterfly block which performs a set of butterfly operations in every clock cycle. From complexity analysis we find that in-place FFT structures with larger butterfly blocks are more efficient in terms of area-time complexity and energy consumption. The resolution of memory access conflict is however more challenging for higher butterfly block sizes. Therefore, we have analyzed the data-flow and memory footprint of in-place RFFT architectures for different throughput requirements, and based on that, we have proposed here a strategy to partition the storage unit into several banks of smaller sizes (without increasing the overall memory size) to resolve the memory access conflicts by concurrent data-swapping between the banks. Synthesis result shows that the proposed structure with butterfly block of size 4 and 8 involves (~44% and ~57%) less area-delay product and (~54% and ~57%) less energy per sample than those of existing similar structure on average for different FFT lengths, respectively.

Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications

Recent advances in mobile computing and multimedia applications demand high - performance and low - power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high - performance applications. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high performance applications. The FIR filter performs the weighted summations of input sequences and is widely used in video convolution functions, signal preconditioning, and various communication applications. Recently, due to the high - performance requirement and increasing complexity of DSP and multimedia communication application. In this work, , FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime.

Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers

Multipliers are the basic building blocks of various processors; arithmetic and logical unit and they are widely used in digital signal processing and image processing applications such as convolution, DWT, DCT. In this paper, four separate algorithms for designing binary multipliers are adopted from the ancient Indian Book of Wisdom Sthapatya-veda (an Upa-veda of Atharvaveda). The current work mainly focuses on comparing the power, delay, look up table (LUT), noise margin of different multiplier algorithms using various sutra's of Vedic mathematics which has been implemented on Virtex 7 Board 1.1, using Xilinx Vivado version 14.2.

Implementation of compressive sampling for wireless sensor network applications

Since mid-20th century, Nyquist-Shannon Sampling Theorem is accepted as we need to sample a signal at twice the max frequency component in order to reconstruct it. Compressive sampling (CS) offers a possible solution of sampling sub-Nyquist and reconstructing using convex programming techniques. There has been significant advancements in CS research and development (more notably since mid-2000s in theory and proofs), but still nothing to the advantage of everyday use. There has been little work on hardware in finding realistic constraints of a working CS system used for digital signal processing (DSP) applications. Parameters used in a system are usually assumed based on stochastic models, but not optimised towards a specific application. This paper aims to address a minimal viable platform to implement compressive sensing if applied to a wireless sensor network (WSN), as well as addressing key parameters of CS algorithms to be determined depending on application requirements and constraints.

Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers

Multipliers are the basic building blocks of various processors; arithmetic and logical unit and they are widely used in digital signal processing and image processing applications such as convolution, DWT, DCT. In this paper, four separate algorithms for designing binary multipliers are adopted from the ancient Indian Book of Wisdom Sthapatya-veda (an Upa-veda of Atharvaveda). The current work mainly focuses on comparing the power, delay, look up table (LUT), noise margin of different multiplier algorithms using various sutra's of Vedic mathematics which has been implemented on Virtex 7 Board 1.1, using Xilinx Vivado version 14.2.

Efficient Floating-Point Division for Digital Signal Processing Application [Tips & Tricks

Floating-point division is an expensive operation for processors in digital signal processing (DSP). The basis of the division operation is finding the reciprocal of the divisor. We present a reciprocal algorithm with four multiplications for single accuracy and six for double accuracy. The algorithm specifically includes bithack (known as magic constant) operations and floating-point addition, multiplication, and the fused multiply-add (fma) operation. The proposed approach improves two characteristics of the division process: accuracy and number of steps. This second characteristic has a direct impact on the division operation performance time and on the amount of equipment required for hardware implementation.

A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders

In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The framework is based on considering the error of approximate adders as an additive noise (approximation noise) that disturbs the output of the DSP block in question. A signal processing theoretical modeling approach for describing the power of the approximation noise which is the integral of error spectral density over the bandwidth, is developed. The output qualities of DSP blocks, such as finite impulse response filter, discrete cosine transform, and fast Fourier transform, which utilize approximate adders, are thus estimated. The accuracy of the proposed framework is evaluated by comparing mathematical model predictions to simulation results by using the signal-to-noise ratio (SNR) metric. The inaccuracy of the SNRs predicted by the framework was, on average, less than 2.5dB compared with that obtained from simulations. Therefore, a mathematical optimization approach based on Lagrange Multipliers for optimizing design parameters is also presented. The optimization is realized by choosing a proper configuration of the target block, such as determining the data width of the inexact computation part for each approximate adder in the design.

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery

Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an $8\times 8$ AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a $16\times 16$ design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

Improving Synchronous Dataflow Analysis Supported by Petri Net Mappings

Whereas most of the work that analyses Synchronous Dataflow (SDF) stays in the dataflow framework, this work pushes its analysis into another framework level, thereby addressing issues that are not well addressed or are even unexplored in SDF. In this manner, the paper proposes a model-driven engineering (MDE) method, combining Synchronous Dataflow (SDF) and Petri nets, to highlight and reinforce their interoperability in digital signal processing applications, cyber-physical systems, or industrial applications. Improvements regarding the settlement and exploitation of the initial conditions associated with SDF are demonstrated; this issue is crucial for every cyber-physical system, since a system’s initial conditions are crucial to ensuring the system’s liveness. The improvements outlined in this work exploit an innovating mapping in the Place/Transition (P/T) Petri net domain that is intended to reduce and predict the total amount of initial data in SDF channels. The relevance of the firing semantics engaged with the equivalent Petri net model is discussed. This paper proposes a new approach to estimate whether an SDF has a static schedule by performing simulation and property verification of the equivalent-based P/T Petri net system achieved, framed by a Petri net invariant analysis and based on the stubborn set method of Petri nets. In this way, this new approach will allow mitigating the state explosion problem. Finally, a strategy is applied to two case studies to discover all the elementary circuits (static schedules) associated with the generated model’s state-space.

A Cross Sectional Study of Tumors Using Bio-Medical Imaging Modalities.

Digital Signal Processing (D.S.P) is an evolutionary field. It has a vast variety of applications in all fields. Bio medical engineering has various applications of digital signal processing. Digital Image Processing is one of the branches of signal processing. Medical image modalities proved to be helpful for disease diagnosis. Higher expertise is required in image analysis by medical professional, either doctors or radiologists. Extensive research is being done and has produced remarkable results. The study is divided into three main parts. The first deals with introduction of mostly used imaging modalities such as, magnetic resonance imaging, x-rays, ultrasound, positron emission tomography and computed tomography. The next section includes explanation of the basic steps of digital image processing are also explained in the paper. Magnetic Resonance imaging modalities is selected for this research paper. Different methods are tested on MRI images. Brain images are selected with and without tumor. Solid cum Cystic tumor is opted for the r esearch. Results are discussed and shown. The software used for digital image processing is MATLAB. It has in built functions which are used throughout the study. The study represents the importance of DIP for tumor segmentation and detection. This study provides an initial guideline for researchers from both fields, that is, medicine and engineering. The analyses are shown and discussed in detail through images. This paper shows the significance of image processing platform for tumor detection automation.