ASIC Research Articles

3x3 array module of 8×8×32 mm3 position-sensitive virtual frisch-grid CdZnTe detectors for imaging and spectroscopy of cosmic gamma-rays

We evaluated the performance of the 3 × 3 array of 32-mm long position-sensitive virtual Frisch-grid (VFG) CdZnTe (CZT) detectors read out by the IDEAS GDS-100 data acquisition system. The array is a mechanically solid module designed for integration into a large effective area gamma-ray telescope proposed for imaging and spectroscopy of cosmic gamma-rays. The array employs the bar-shaped 8 × 8 × 32 mm3 CZT crystals which recently became available from Redlen Technologies, Inc. and Kromek-eV Group PLC at affordable costs. The waveform sampling IDE3421 application-specific integrated circuit (ASIC), developed by the University of Michigan and IDEAS for CZT pixel detectors, was adapted to capture the signals from the array's VFG detectors. We showed good spectral performance of the Redlen detectors with an energy resolution of <1% FWHM at 662 keV and slightly poorer performance of the Kromek-eV detectors with a resolution of <2% measured at a reduced temperature of 13 °C. By testing the same detectors as single devices using hybrid charge-sensitive preamplifiers, we demonstrated improved energy resolutions at a normal temperature of ∼25 °C: <1% and 1.3–1.7%, respectively. However, the Kromek-eV detectors did not perform as well as the Redlen ones. We explained this by the space charge formation (polarization) decreasing the electric field and the electron drift times. The polarization was likely caused by the high injections of holes from the anode contacts. The absence of polarization in Redlen detectors suggested that the quality of the contacts might have played a role in this case.

Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution

We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.

Technology independent optimization when implementing sparse systems of disjunctive normal forms of Boolean functions in ASIC

Objectives. The problem of choosing the best methods and programs for circuit implementation as part of digital ASIC (Application-Specific Integrated Circuit) sparse systems of disjunctive normal forms (DNF) of completely defined Boolean functions is considered. For matrix forms of sparse DNF systems, the ternary matrix specifying elementary conjunctions contains a large proportion of undefined values corresponding to missing literals of Boolean input variables, and the Boolean matrix specifying the occurrences of conjunctions in DNF functions contains a large proportion of zero values.Methods. It is proposed to investigate various methods of technologically independent logical optimization performed at the first stage of logical synthesis: joint minimization of systems of functions in the DNF class, separate and joint minimization in classes of multilevel representations in the form of Boolean networks and BDD representations using mutually inverse cofactors, as well as the division of a system of functions into subsystems with a limited number of input variables and the method of block cover of DNF systems, focused on minimizing the total area of the blocks forming the cover.Results. When implementing sparse DNF systems of Boolean functions in ASIC, along with traditional methods of joint minimization of systems of functions in the DNF class, methods for optimizing multilevel representations of Boolean function systems based on Shannon expansions can be used for technologically independent optimization, while separate minimization and joint minimization of the entire system as a whole turn out to be less effective compared with block partitions and coatings of the DNF system and subsequent minimization of multilevel representations. Schemes obtained as a result of synthesis using minimized representations of Boolean networks often have a smaller area than schemes obtained using minimized BDD representations.Conclusion. For the design of digital ASIC, the effectiveness of combined approach is shown, when initially the block coverage programs of the DNF system is used, followed by the use of programs to minimize multilevel block representations in the form of Boolean networks minimized based on Shannon expansion.

Accelerating range minimum queries with ray tracing cores

Over the past decade, GPU technology has undergone a notable transformation, evolving from pure general-purpose computation to the integration of application-specific integrated circuits (ASICs), including Tensor Cores and Ray Tracing (RT) cores. While these specialized GPU cores were initially developed to enhance specific domains like AI and real-time rendering, recent research has successfully harnessed their capabilities to expedite other tasks traditionally reliant on conventional GPU computing. One GPU task that is still yet to find its way into RT cores is the processing of range minimum queries (RMQs) in parallel, which is fundamental in fields such as information retrieval or pattern matching, among others. In this context, accelerating RMQs with RT cores would impact many of the applications that heavily rely on this task. In this work we present RTXRMQ, a new approach that can compute RMQs with RT cores. The main contribution is the proposal of a geometric solution for RMQ, where elements become triangles that are placed and shaped according to the element’s value and position in the array, respectively, such that the closest hit of a ray launched from a point given by the query parameters corresponds to the result of that query. Experimental results show that RTXRMQ is currently best suited for small query ranges relative to the input size, achieving up to 5× and 2.3× of speedup over parallel state of the art CPU and GPU approaches, respectively. For medium and large query ranges RTXRMQ is still slower than the state of the art GPU approach, but still competitive by being 2.5× and 4× faster than a state of the art CPU method running in parallel as well. Furthermore, performance scaling experiments across the latest RTX GPU architectures show that if the current RT core scaling trend continues, then RTXRMQ’s performance would scale at a higher rate than the other compared approaches, making it an attractive tool for future high performance applications that employ many batches of RMQs.

Revolutionizing machine learning: A comprehensive analysis of ASIC hardware accelerators and their applications

The growth of the web over the past few years has led to tremendous data growth, which has provided a powerful impetus for artificial intelligence and machine learning. Machine learning algorithms are widely used in various classification and prediction problems. However, with the rich data types and needs, the traditional software computing method that relies on CPU can no longer meet the application scenarios under different requirements. Machine Learning (ML) hardware accelerators, especially Application Specific Integrated Circuits (ASICs), have become trendy to meet a variety of needs. This paper reviews the research on ML ASIC in the past few years, reviews the development of ML and ASIC design, and summarizes the characteristics of their use. It is followed by examples of various scenarios for which it can be used, such as medical diagnostics and internet of thing (IOT) terminals. Finally, the author analyses the existing problems and limitations, and gives the improvement methods of hardware and algorithm to deal with the related obstacles. It is hoped that this paper can provide some help and convenience for the subsequent related research.

Unveiling the powerhouses of AI: A comprehensive study of GPU, FPGA, and ASIC accelerators

In the ever-evolving realm of technology, Artificial Intelligence (AI) has ushered in a transformative era, reshaping our interactions with digital systems, and expanding the horizons of machine capabilities. At the core of this AI revolution are specialized hardware entities known as AI accelerators. These accelerators, including Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs), play a pivotal role in advancing AI applications across diverse domains. This paper delves into these accelerators, offering an in-depth exploration of their unique attributes and application domains. GPUs, initially designed for graphics, have evolved into versatile tools, thanks to their parallel computing prowess and efficient memory utilization. FPGAs, with reconfigurability and low latency, prove valuable in aerospace and neural network implementations, though they come with cost and expertise challenges. ASICs, engineered for specific functions, excel in performance and power efficiency for mass production but require significant time and resources for development. Furthermore, this paper presents practical application analyses, showcasing how these accelerators are effectively deployed in real-world scenarios. With this comprehensive exploration, readers gain a deeper understanding of AI accelerators and their transformative impact on the AI landscape.

A Low-Intensity Pulsed Ultrasound Interface ASIC for Wearable Medical Therapeutic Device Applications

Low-intensity pulsed ultrasound (LIPUS) is a non-invasive medical therapy that has attracted recent research interest due to its therapeutic effects. However, most LIPUS driver systems currently available are large and expensive. We have proposed a LIPUS interface application-specific integrated circuit (ASIC) for use in wearable medical devices to address some of the challenges related to the size and cost of the current technologies. The proposed ASIC is a highly integrated system, incorporating a DCDC module based on a charge pump architecture, a high voltage level shifter, a half-bridge driver, a voltage-controlled oscillator, and a corresponding digital circuit module. Consequently, the functional realization of this ASIC as a LIPUS driver system requires only a few passive components. Experimental tests indicated that the chip is capable of an output of 184.2 mW or 107.2 mW with a power supply of 5 V or 3.7 V, respectively, and its power conversion efficiency is approximately 30%. This power output capacity allows the LIPUS driver system to deliver a spatial average temporal average (SATA) of 29.5 mW/cm2 or 51.6 mW/cm2 with a power supply of 3.7 V or 5 V, respectively. The total die area, including pads, is 4 mm2. The ASIC does not require inductors, improving its magnetic resonance imaging (MRI) compatibility. In summary, the proposed LIPUS interface chip presents a promising solution for the development of MRI-compatible and cost-effective wearable medical therapy devices.

Revolutionizing machine learning: Harnessing hardware accelerators for enhanced AI efficiency

In recent decades, the field of Artificial Intelligence (AI) has undergone a remarkable evolution, with machine learning emerging as a pivotal subdomain. This transformation has led to increasingly complex algorithms and soaring data volumes, necessitating robust computational resources. Conventional central processing units (CPUs) are struggling to meet the demanding requirements of modern AI applications. In response to this computational challenge, a new generation of hardware accelerators has been developed to enhance the processing and learning capabilities of machine learning systems. Graphics Processing Units (GPUs), Tensor Processing Units (TPUs), and Application Specific Integrated Circuits (ASICs) are among the specialized accelerators that have emerged. These hardware accelerators have proven instrumental in significantly improving the efficiency of machine learning tasks. This paper provides a comprehensive exploration of these hardware accelerators, offering insights into their design, functionality, and applications. Moreover, it examines their role in empowering machine learning processes and discusses their potential impact on the future of AI. By addressing current trends and anticipated challenges, this paper contributes to a deeper understanding of the dynamic landscape of hardware acceleration in the context of machine learning research and development.

Power-aware high-capacity elastic optical networks

The power consumption of telecommunication equipment has been identified as a relevant contributor to global energy consumption. In fact, new-generation optical transponders employ power-intensive electronic application-specific integrated circuits (ASICs) for digital signal processing (DSP). DSP design has traditionally prioritized meeting transmission requirements over power consumption optimization. In general, the evolutions of transmission techniques and network design have always been mainly driven by traffic increase; in this context, in order to operate network resources more efficiently, margin reduction has been investigated in the past few years. Indeed, traditionally, high physical layer margins are used to ensure reliability over an extended period, resulting in overprovisioning the optical connections for both physical layer conditions and capacity. On the other hand, super-channels have emerged as a suitable solution for accommodating the continuous traffic growth. However, power consumption has not been deeply considered in the optimization of super-channel transmission. This paper first investigates the power efficiency of super-channels operated with designed and reduced margins. Low-margin operation is enabled by adapting sub-carrier spacing and filter bandwidth. Power-aware super-channel optimization is then experimentally demonstrated leveraging a 600 Gbit/s transponder in the SDN-controlled elastic optical network (EON). The results have identified a trade-off between power consumption and spectrum efficiency. Furthermore, the ongoing bandwidth demand has motivated the investigation of multi-band (MB) transmission for scaling the capacity of the existing infrastructures. However, novel networking devices (e.g., optical amplifiers operating beyond the C- and L-bands) will affect the overall power consumption. In this context, experimental power analysis of a thulium doped fiber amplifier (TDFA) is performed based on the traffic load and corresponding configuration. The results show that TDFA power consumption varies with configuration and increases with output power.

Precise and low-power closed-loop neuromodulation through algorithm-integrated circuit co-design.

Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson's disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closed-loop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm2 silicon area and the average power consumption is 142 μW. The proposed solution achieves a significant reduction in both false alarm rates and power consumption when benchmarked against state-of-the-art counterparts.

The LHCb VELO Upgrade II: Design and development of the readout electronics

In 2032–2034, the LHCb will be upgraded to efficiently explore the new HL-LHC conditions. The increased number of interactions per event and radiation level brings several challenges including high non-uniform radiation doses (up to 6×1016MeVneq/cm2), operation under vacuum (power dissipation below 1.5 W/cm2), high data rates (up to order of 100 Gbps/ASIC) and ASIC timing resolution (30 ps or better). This proceedings describes the requirements for two different upgrade scenarios (different pixel pitch, radiation doses and material budget while keeping the same scattering terms), application specific integrated circuit status to readout the sensor pixels (PicoPix and IGNITE), electronic integration (Anisotropic Conductive Bonding) and data transmission (FALAPHEL). In summary, the open challenges mentioned before are being addressed in the current R&D phase and the most suitable candidate solutions will be consolidated in the technical design report in the coming years.

Plant Disease Identification Using Machine Learning Algorithms on Single-Board Computers in IoT Environments

This paper investigates the usage of machine learning (ML) algorithms on agricultural images with the aim of extracting information regarding the health of plants. More specifically, a custom convolutional neural network is trained on Google Colab using photos of healthy and unhealthy plants. The trained models are evaluated using various single-board computers (SBCs) that demonstrate different essential characteristics. Raspberry Pi 3 and Raspberry Pi 4 are the current mainstream SBCs that use their Central Processing Units (CPUs) for processing and are used for many applications for executing ML algorithms based on popular related libraries such as TensorFlow. NVIDIA Graphic Processing Units (GPUs) have a different rationale and base the execution of ML algorithms on a GPU that uses a different architecture than a CPU. GPUs can also implement high parallelization on the Compute Unified Device Architecture (CUDA) cores. Another current approach involves using a Tensor Processing Unit (TPU) processing unit carried by the Google Coral Dev TPU Board, which is an Application-Specific Integrated Circuit (ASIC) specialized for accelerating ML algorithms such as Convolutional Neural Networks (CNNs) via the usage of TensorFlow Lite. This study experiments with all of the above-mentioned devices and executes custom CNN models with the aim of identifying plant diseases. In this respect, several evaluation metrics are used, including knowledge extraction time, CPU utilization, Random Access Memory (RAM) usage, swap memory, temperature, current milli Amperes (mA), voltage (Volts), and power consumption milli Watts (mW).

Characterisation of a customised 4-chip Timepix3 module for charged-particle tracking

Ion-beam radiotherapy is a growing cancer treatment modality because it offers a superior dose distribution in the patient compared with conventional radiotherapy using X-rays. Thanks to their versatility, application-specific integrated circuits (ASIC) increasingly gain interest for research into ion imaging and ion-beam characterisation. Timepix3 is a hybrid semiconductor pixel detector, which offers nanosecond time binning as well as dead-time-free and noise-free data-driven readout at a pixel pitch of 55µm × 55µm. In this work, a novel 4-chip Timepix3 mini-tracker (quad module) was characterised in a therapeutic proton beam. The quad module has two detection layers equipped with two Timepix3 chips each, which are stacked like a particle telescope at a distance of 20.3mm. In a detection layer, two Timepix3 chips share the same sensitive silicon sensor. The surface area of the silicon sensor is approximately 28mm × 14mm. Apart from the pixels at the chip edges and the masked pixels, the quad module showed a uniform counting response to the mono-energetic proton irradiation without noticeable defects. The measurement accuracy of the energy deposition was found to be better than 1% at 340keV. The synchronisation between the four chips of the quad module showed systematic delays of up to 25ns. When these delays are corrected, the time resolution of the quad module is (1.17 ± 0.03)ns. The time resolution could be further improved with the implementation of a time-walk correction. It is concluded that the quad module fulfils the requirements to be used as a charged-particle tracker in ion-beam radiotherapy. Future testing will focus on the radiation hardness, dose-rate dependence and response to high-LET radiation.

Deposition of Fine-Pitch Indium Bumps on Single Die

Photolithographic lift-off at wafer level is a wellestablished method for depositing indium bumps onto pixels of electronic components such as sensors and application-specific integrated circuits (ASIC). These indium bumps form interconnects between pixels of the components during flip-chip bonding to make devices such as radiation detectors. Such components are not always available on wafer-scale, and single dies need to be processed in small-scale production, R&amp;D, or for Cd(Zn)Te detector material. Photolithography on single dies is ineffective due to the edge-bead of photoresist that compromises perfect indium deposition onto pixels near the periphery of the die. To utilize the maximum surface area of a die, a rigid mask with apertures (shadow mask) is an adequate substitute for the photoresist. Different mask designs and production techniques for fine-pitch indium bump arrays are investigated by testing electroformed stencils or micromachined silicon (Si) membranes as shadow masks. For the indium deposition, the sensor and ASIC dies are clamped into custom-made jigs that include shadow masks. Alternatively, dies can be adhered to shadow masks with soluble adhesive. The apertures of a mask are aligned to the pixel array of the detector component. Bump arrays with 250μm- and 100μm-pitch were demonstrated with electroformed stencils. For smaller pitch (55μm) and bump diameter of ~20μm, specialized masks from Si membranes are tested. Components with successfully deposited indium bump arrays were subsequently flip-chip bonded at room temperature without reflowing the indium. A bond yield of at least 99.9% pixels for such flip-chip bonded radiation detector was shown using the read-out signal from exposure with a flat field X-ray radiation of an Am-241 sealed source.

Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately ∼\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\sim$$\\end{document}1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of ∼\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\sim$$\\end{document}4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits.

The CMS Fast Beam Condition Monitor for HL-LHC

The high-luminosity upgrade of the LHC brings unprecedented requirements for real-time and precision bunch-by-bunch online luminosity measurement and beam-induced background monitoring. A key component of the CMS Beam Radiation, Instrumentation and Luminosity system is a stand-alone luminometer, the Fast Beam Condition Monitor (FBCM), which is fully independent from the CMS central trigger and data acquisition services and able to operate at all times with a triggerless readout. FBCM utilizes a dedicated front-end application-specific integrated circuit (ASIC) to amplify the signals from CO2-cooled silicon-pad sensors with a timing resolution of a few nanoseconds, which enables the measurement of the beam-induced background. FBCM uses a modular design with two half-disks of twelve modules at each end of CMS, with four service modules placed close to the outer edge to reduce radiation-induced aging. The electronics system design adapts several components from the CMS Tracker for power, control and read-out functionalities. The dedicated FBCM23 ASIC contains six channels and adjustable shaping time to optimize the noise with regards to sensor leakage current. Each ASIC channel outputs a single binary high-speed asynchronous signal carrying time-of-arrival and time-over-threshold information. The chip output signal is digitized,encoded, and sent via a radiation-hard gigabit transceiverand an optical link to the back-end electronics for analysis. This paper reports on the updated design of the FBCM detector and the ongoing testing program.

Cryogenic acoustic microscopy and evaulation of electronic components

Electronics operating at cryogenic temperatures are essential in fields like space exploration and particle physics. The Deep Underground Neutrino Experiment (DUNE), a next generation particle physics experiment, will rely on tens of thousands of custom designed application specific integrated circuits (ASICs) operating directly in liquid argon (87 K) for decades without repair or replacement. Ensuring circuit functional reliability throughout the duration of the experiment is mission critical. Both functional and nondestructive testing are employed to safeguard circuit quality and reliability. Part of this work involves the design, testing, and data analysis of a cryogenic acoustic microscope (CryoSAM) operating at 15 MHz. The CryoSAM is capable of interrogating ASICs at both room temperature (300 K) and in liquid nitrogen (77 K), identifying acoustic anomalies likely arising from thermal stress and manufacturing-related defects, using a powerful correlation analysis technique. These anomalies can lead to functional degradation and suboptimal electronic performance of the circuit sensors. Image analysis and correlations are used to compare differences seen before and after cryogenic temperature cycling. Data are reported that were collected at both room temperature and when cooled using liquid nitrogen. Designs and challenges of operating the instrument at cryogenic temperatures are also discussed.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

An 8-channel low power ASIC for Helium-3 tube position sensitive neutron detectors

The majority of neutron spectrometers designated for use in the China Spallation Neutron Source (CSNS) rely on position-sensitive detectors that utilize Helium-3 tube detector technology. To minimize the impact of air on neutron scattering experiments, detectors must be located inside a vacuum chamber. For these types of spectrometers, it is also advisable to house the readout electronics within the vacuum chamber to limit the number of feed-through cables required and enhance the signal-to-noise ratio. This paper proposes an application-specific integrated circuit (ASIC) dedicated to position-sensitive Helium-3 tube detectors, including front-end amplification, shaping module and readout driving buffer. The 8-channel chip, named HEROCV1 (HElium-3 ReadOut Circuits), achieves an input dynamic range from 10 fC to 1 pC, with a counting rate of up to 100 kHz. The equivalent noise charge (ENC) measurement is 1297e-@15pF, and the power consumption is less than 9.9 mW per channel. The ASIC has replaced the traditional front-end circuit based on discrete components, fundamentally addressing the issue of front-end power consumption and enabling the entire detector system to operate in a vacuum environment.

Neural network methods for radiation detectors and imaging

Recent advances in image data proccesing through deep learning allow for new optimization and performance-enhancement schemes for radiation detectors and imaging hardware. This enables radiation experiments, which includes photon sciences in synchrotron and X-ray free electron lasers as a subclass, through data-endowed artificial intelligence. We give an overview of data generation at photon sources, deep learning-based methods for image processing tasks, and hardware solutions for deep learning acceleration. Most existing deep learning approaches are trained offline, typically using large amounts of computational resources. However, once trained, DNNs can achieve fast inference speeds and can be deployed to edge devices. A new trend is edge computing with less energy consumption (hundreds of watts or less) and real-time analysis potential. While popularly used for edge computing, electronic-based hardware accelerators ranging from general purpose processors such as central processing units (CPUs) to application-specific integrated circuits (ASICs) are constantly reaching performance limits in latency, energy consumption, and other physical constraints. These limits give rise to next-generation analog neuromorhpic hardware platforms, such as optical neural networks (ONNs), for high parallel, low latency, and low energy computing to boost deep learning acceleration (LA-UR-23-32395).