Application Specific Integrated Circuit Implementation Research Articles

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

High‐performance elliptic curve cryptography processor over NIST prime fields

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224-bit and 256-bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area-efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area–delay product of this design is very low compared with similar designs. To the best of the authors’ knowledge, the ECP proposed in this study over F p performs better than available hardware in terms of area and timing.

Very large scale integration architecture for block‐matching motion estimation using adaptive rood pattern search algorithm

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 µm) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm2. A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 × 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 × 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 × 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

ASIC Implementation of High throughput FFT Processor for Scientific Applications

Objectives: This paper aims at designing high speed and high throughput Fast Fourier Transform (FFT) processor which is a critical block and is widely used in many Digital Signal Processing applications. Methods: The proposed model works with both real and complex type of input data. Pipelining in the proposed architecture is achieved with single delay feedback methodology. Findings: The CMOS 0.18 µm is used to design Application Specific Integrated Circuit (ASIC) for the proposed FFT processor and it works with an input size of 36 bits at the operating frequency of 100 MHz, occupies an area of 1.27 mm and consumes 39 mW, at an operating voltage of 1.8V.Obtained results are compared with existing methods in terms of input word length, throughput, power dissipation and it shows that the proposed architecture gives high throughput, uses 3x more word length and 2x less power dissipation. Applications: The designed chip can be used in scientific computations since it require less power and operates in high speed.

Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC) platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

System On Chip (SOC) ASIC chipset for Smart Actuators in Distributed Propulsion Systems

Abstract This paper describes the results of the risk reduction testing task recently completed by Embedded Systems LLC under the Air Force SBIR contract {5} titled “Improved Full Authority Digital Engine Control (FADEC) System”. The objective of this program has been to develop a hierarchical, distributed architecture for future propulsion FADEC and aerospace control systems with flexible, scalable and reconfigurable Smart Nodes (SN) built with high temperature capable devices. A key part of this program is the design, development and validation of the System On Chip (SOC) chipset in high temperature (225 Deg. C) SOI (Silicon On Insulator) technology ASIC (Application Specific Integrated Circuit) devices. The SOC chipset designed by Embedded Systems LLC provides the scalability and reconfigurability that enables the Smart Node to interfaces with most sensors and actuators found in FADEC and other aircraft control systems. The analog portion of this 2-chip SOC chipset fabricated by Honeywell using their SOI process is working properly. The digital portion of the SOC chipset, currently implemented in a commercial temperature FPGA (Field Programmable Gate Array), contains important computational functions needed for reconfiguring the SOC and performing complex control functions, such as real time control of an actuator, The risk reduction task was therefore focused on verification and validation of these key functions in a real environment before converting the design into an ASIC. The recent successful demonstration of the real time actuator control capability has minimized the risks and cleared the way for the digital ASIC implementation. The complete high temperature SOC chipset is expected to be available in late 2016.

On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

Many recent advances in sparse coding led its wide adoption in signal processing, pattern classification, and object recognition applications. Even with improved performance in state-of-the-art algorithms and the hardware platform of CPUs/GPUs, solving a sparse coding problem still requires expensive computations, making real-time large-scale learning a very challenging problem. In this paper, we cooptimize algorithm, architecture, circuit, and device for real-time energy-efficient on-chip hardware acceleration of sparse coding. The principle of hardware acceleration is to recognize the properties of learning algorithms, which involve many parallel operations of data fetch and matrix/vector multiplication/addition. Today's von Neumann architecture, however, is not suitable for such parallelization, due to the separation of memory and the computing unit that makes sequential operations inevitable. Such principle drives both the selection of algorithms and the design evolution from CPU to CMOS application-specific integrated circuits (ASIC) to parallel architecture with resistive crosspoint array (PARCA) that we propose. The CMOS ASIC scheme implements sparse coding with SRAM dictionaries and all-digital circuits, and PARCA employs resistive-RAM dictionaries with special read and write circuits. We show that 65 nm implementation of the CMOS ASIC and PARCA scheme accelerates sparse coding computation by $394$ and $2140\times$ , respectively, compared to software running on a eight-core CPU. Simulated power for both hardware schemes lie in the milli-Watt range, making it viable for portable single-chip learning applications.

Design and Implementation of Booth Multiplier using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. Keyword: Approximate computing, low power, mirror adder. Booths multiplier, Wallace tree multiplier I. INTRODUCTION Digital signal processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. Most of these DSP blocks implement image and video processing algorithms, where the ultimate output is either an image or a video for human consumption. Human beings have limited perceptual abilities when interpreting an image or a video. This allows the outputs of these algorithms to be numerically approximate rather than accurate. This relaxation on numerical exactness provides some freedom to carry out imprecise or approximate computation. We can use this freedom to come up with low-power designs at different levels of design abstraction, namely, logic, architecture, and algorithm. The paradigm of approximate computing is specific to select hardware implementations of DSP blocks. It is shown in (1) that an embedded reduced instruction set computing processor consumes 70% of the energy in supplying data and instructions, and 6% of the energy while performing arithmetic only. Therefore, using approximate arithmetic in such a scenario will not provide much energy benefit when considering the complete processor. Programmable processors are designed for general-purpose applications with no application-specific specialization. Therefore, there may not be many applications that will be able to tolerate errors due to approximate computing. This also makes general-purpose processors not suited for using approximate building blocks. This issue has already been discussed in (13). Therefore, in this paper, we consider application-specific integrated circuit implementations of error-resilient applications like image and video compression.

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

SummaryThis paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi‐input multi‐output (MIMO) piecewise‐affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90‐nm complementary metal‐oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high‐performance and minimum unitary cost are required. Copyright © 2015 John Wiley &amp; Sons, Ltd.

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

Redundant basis (RB) multipliers over Galois Field ( GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> )) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper, we have proposed a novel recursive decomposition algorithm for RB multiplication to obtain high-throughput digit-serial implementation. Through efficient projection of signal-flow graph (SFG) of the proposed algorithm, a highly regular processor-space flow-graph (PSFG) is derived. By identifying suitable cut-sets, we have modified the PSFG suitably and performed efficient feed-forward cut-set retiming to derive three novel multipliers which not only involve significantly less time-complexity than the existing ones but also require less area and less power consumption compared with the others. Both theoretical analysis and synthesis results confirm the efficiency of proposed multipliers over the existing ones. The synthesis results for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) realization of the proposed designs and competing existing designs are compared. It is shown that the proposed high-throughput structures are the best among the corresponding designs, for FPGA and ASIC implementation. It is shown that the proposed designs can achieve up to 94% and 60% savings of area-delay-power product (ADPP) on FPGA and ASIC implementation over the best of the existing designs, respectively.

Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression

Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition

The processing capabilities that are included into the acquisition block of the real-time digital oscilloscopes largely contribute to determine the overall performance of the instrument. Their remarkable improvement has made it possible to enhance the performance in terms of increased measurement rate, automation, and reduced measurement uncertainty related to quantization and noise. This paper presents the implementation of a preprocessing circuit for a novel acquisition mode of bandpass signals, which is characterized by an increased vertical resolution. Although the theoretical foundations were recently presented with simulative results, here, the circuital implementation of such an acquisition mode is presented. The focus is on mid or low cost digital oscilloscopes that can improve their vertical resolution at a negligible additional cost. First, a preliminary field programmable gate array implementation is considered to evaluate the achievable performance both from a theoretical point of view and throughout experimental tests. Then, a custom application specific integrated circuit implementation, in 28-nm complementary metal-oxide-semiconductor technology is analyzed. Along with the parameter optimization, the work experimentally tests the acquisition mode and evaluates the effects of nonideal characteristics such as finite word length and nonideal filtering. The increase in the effective number of bit (ENoB) is up to 2.5 bit, whereas the ENoB degradation because of word length and nonideal filtering is quantified as ~ 1.1 and 0.5 bit. The design highlights that there is substantial margin for parallel implementation that is the base to candidate the proposed solution as a remarkable option for the next generation oscilloscopes.

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions

This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.

A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9, 7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65 nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486 MHz with a power consumption of 2.56 mW. This architecture is suitable for real-time video compression even with large frame dimensions.

Blind channel estimation for MLSE receiver in high speed optical communications: theory and ASIC implementation

Blind channel estimation is critical for digital signal processing (DSP) compensation of optical fiber communications links. The overall channel consists of deterministic distortions such as chromatic dispersion, as well as random and time varying distortions including polarization mode dispersion and timing jitter. It is critical to obtain robust acquisition and tracking methods for estimating these distortions effects, which, in turn, can be compensated by means of DSP such as Maximum Likelihood Sequence Estimation (MLSE). Here, a novel blind estimation algorithm is developed, accompanied by inclusive mathematical modeling, and followed by extensive set of real time experiments that verify quantitatively its performance and convergence. The developed blind channel estimation is used as the basis of an MLSE receiver. The entire scheme is fully implemented in a 65 nm CMOS Application Specific Integrated Circuit (ASIC). Experimental measurements and results are presented, including Bit Error Rate (BER) measurements, which demonstrate the successful data recovery by the MLSE ASIC under various channel conditions and distances.

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing need for domain-specific acceleration technologies, this paper describes a design methodology (i) to automatically generate a domain-specific coarse-grained array from a set of representative applications and (ii) to introduce limited forms of architectural generality to increase the likelihood that additional applications can be successfully mapped onto it. In particular, coarse-grained arrays generated using our approach are intended to be integrated into customizable processors that use application-specific instruction set extensions to accelerate performance and reduce energy; rather than implementing these extensions using application-specific integrated circuit (ASIC) logic, which lacks flexibility, they can be synthesized onto our reconfigurable array instead, allowing the processor to be used for a variety of applications in related domains. Results show that our array is around 2× slower and 15× larger than an ultimately efficient ASIC implementation, and thus far more efficient than fieldprogrammable gate arrays (FPGAs), which are known to be 3-4× slower and 20-40× larger. Additionally, we estimate that our array is usually around 2× larger and 2× slower than an accelerator synthesized using traditional datapath merging, which has, if any, very limited flexibility beyond the design set of DFGs.

Symbol Spaced Adaptive MIMO Equalization for Ultrahigh Bit Rate Metro Coherent Optical Links

A novel approach to symbol spaced adaptive multiple-input-multiple-output (MIMO) equalization is proposed. Different functionalities are defined for static versus adaptive equalizers, to minimize noise enhancement. Static equalizers are used for anti-aliasing filtering and bulk CD compensation, and a newly proposed modified-LMS-based adaptive MIMO equalizer is used to compensate for fiber random impairments such as residual CD and PMD. In addition, the proposed technique enables the use of low-cost reduced bandwidth components in both transmit and receive sides, and supports aggressive in-line optical filtering in the existing WDM network. Moreover, the proposed technique perfectly suits coherent metro applications, allowing significant power savings in application specific integrated circuit implementation.

Implementation of comprehensive address generator for digital signal processor

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log 2 N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.

Application Specific Integrated Circuit Implementation of Discrete Fractional Fourier Transform

Over the last two decades, discrete fractional Fourier transform (DFrFT), which is a generalization of the discrete Fourier transform (DFT), has attracted a lot of attention of the researchers. Several methods for computation of the DFrFT have been discussed in the literature but very little effort has been made towards realizing a dedicated hardware for its real time computation. In this paper we propose an application specific integrated circuit (ASIC) design for 16-point DFrFT computation of a 1D signal, which has been synthesized using Very High Speed Integrated Circuit hardware description language (VHDL). The same design can be easily extended for any number of signal samples. The simulation results of the proposed ASIC are very close to the theoretical DFrFT results obtained using the MATLAB software.

Theory and verification of operator design methodology

Non-recurring-engineering (NRE) and time-to-market play an increasingly important role in the field of IC design. Meanwhile, with the continuous development of IC manufacturing technology, it is necessary to propose a novel design methodology to shorten design cycle and enhance design efficiency. In this paper, operator design methodology (ODM) is presented and an H.264 encoder is implemented as a verification. According to the flow of ODM, the register transfer level (RTL) design of H.264 encoder has been accomplished with 15 manmonths, which is lower than the average 19 man-months in the field of traditional application specific integrated circuit (ASIC) design. Moreover, with the advantage of operator design library, the design has a comparable performance with other ASIC implementations. The obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 30 frames per second, working at 167 MHz with SMIC 0.13 μm CMOS technology. These results provide good evidence for the practicability and efficiency of ODM.