Abstract
An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC) platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.
Highlights
Arithmetic Logic Unit (ALU) DESIGN- VERIFICATIONInitial verification of both the ALUs i.e. ALU-RCA and ALU-SKL were performed based on the waveform approach using ModelSim software tool [47] as we made both the ALUs generic so we reduced the ALU size to 8-bit just to make initial verification simple
An Arithmetic Logic Unit (ALU) is key the element of a processor which performs arithmetic and logical operations on binary numbers [1-7]
The two ALU units were implemented in VHDL using Ripple Carry Adder and Sklansky Adder circuits
Summary
Initial verification of both the ALUs i.e. ALU-RCA and ALU-SKL were performed based on the waveform approach using ModelSim software tool [47] as we made both the ALUs generic so we reduced the ALU size to 8-bit just to make initial verification simple. The waveform based approach of verification is only useful during the initial phases of small designs and always requires more comprehensive verification in the later design stages. There were some small bugs found in the code which were later corrected
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