A Dynamical Machine Control System using Simple Processing Unit Based-on FPGA

Abstract

This paper aims to design a dynamic machine control system device. The proposed dynamic device models are a combination architecture of memory and Arithmetic-Logic Unit (ALU). The configuration of the memory has used a random access memory (RAM), and the configuration of ALU is the core of the central processing unit (CPU), which consists of two functions, namely the arithmetic unit and the logical unit. In this paper, the arithmetic unit consists of addition, subtraction, multiplication, and division, whereas the logical units are AND, OR, NOT, and XOR. The shifter circuit in this paper was also applied to complete the programming code instructions in a software approach. The arithmetic unit and logic unit selector path in the ALU configuration employed a multiplexer circuit. This paper used a top-down design technique by determining the components in implementation. By knowing the function and work of these components, it is much easier to combine the components employing the configuration code of the hardware description language, namely a Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The implementation of the VHDL code was configured into the Xilinx Spartan-3E Field Programmable Gate Array (FPGA) to determine the component consumption and the resulted delay time. The results obtained from the configuration of the ALU components consume 26 slices, 50 4-input look-up table (LUT), 17 input/output (I/O), and 17 Bonded IO, while the component delay time is 11,413 ns.