Application Specific Integrated Circuit Implementation Research Articles

Hamming Distance Model Based Power Analysis for Cryptographic Algorithms

In order to evaluate the security of Application Specific Integrated Circuit (ASIC) implemented cryptographic algorithms at an early design stage, a Hamming distance model based power analysis is proposed. The Data Encryption Standard (DES) algorithm is taken as an example to illustrate the threats of differential power analysis (DPA) attack against the security of ASIC chip. A DPA attack against the ASIC implementation of a DES algorithm is realized based on hamming distance power model (HD model), and it realized the attack by successfully guessing the right 48-bit subkey. This result indicates that the power analysis attack based on the HD model is simple, rapid and effective for the design and evaluation of security chips.

High-Speed Algorithms and Architectures for Range Reduction Computation

Range reduction is a crucial step for accuracy in trigonometric functions evaluation. This paper shows and compares a set of algorithms for additive range reduction computation and their corresponding application-specific integrated circuit implementations (ensuring an accuracy of one unit in the last place). A word-serial architecture implementation has been used as a reference for clearer comparisons. Besides, a new table-based pipelined architecture for range reduction has also been proposed.

Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.

Optimized hardware architecture for object recognition and tracking

The recent research is focused on development of mobile vision systems and algorithms suitable for very large-scale integration implementation. These systems can be used in various applications. We propose a novel field-programmable gate array (FPGA)-based architecture for early vision. The central idea is to take into account the perceptual aspects of visual tasks inspired by biological vision systems: shape and color. For this reason, we propose an original approach based on a system implemented in an FPGA connected to a CMOS imager. The proposed algorithm implementation analysis and optimization methodology under resource constraints enable one to implement the algorithm on only one FPGA chip. To prove the proposed concept the system was implemented and tested on an autonomous mobile platform. The implementation framework enables direct algorithm implementation in application-specific integrated circuit.

FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria

Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130 nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC.

An FPGA-Based Network Intrusion Detection Architecture

Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit networks, current generation networking components for NIDS will soon be insufficient for numerous reasons; most notably because the existing methods cannot support high-performance demands. Field-programmable gate arrays (FPGAs) are an attractive medium to handle both high throughput and adaptability to the dynamic nature of intrusion detection. In this work, we design an FPGA-based architecture for anomaly detection in network transmissions. We first develop a feature extraction module (FEM) which aims to summarize network information to be used at a later stage. Our FPGA implementation shows that we can achieve significant performance improvements compared to existing software and application-specific integrated-circuit implementations. Then, we go one step further and demonstrate the use of principal component analysis as an outlier detection method for NIDSs. The results show that our architecture correctly classifies attacks with detection rates exceeding 99% and false alarms rates as low as 1.95%. Moreover, using extensive pipelining and hardware parallelism, it can be shown that for realistic workloads, our architectures for FEM and outlier analysis achieve 21.25- and 23.76-Gb/s core throughput, respectively.

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.

FPGA vs. ASIC for low power applications

Field Programmable Gate Array (FPGA) are becoming more and more popular and are used in many applications. However, it is well known that the performance is limited comparing to full ASIC implementation, but for many applications the speed requirements fit the ones provided already by existing FPGA circuits. Power consumption seems to be one of the most important limiting factor and so far it is in favour of Application Specific Integrated Circuits (ASIC) [Varghese Georges, Jan M. Rabaey, Low-Energy FPGA, Architecture and Design, Kluwer Academic Publishers, 2001; Tadahiro Kuroda, Power-Aware Electronics: Challenges and Opportunities, Tutorial at FTFC 2003, Paris, May 2003]. In this paper, we will present results obtained by characterizing various circuits implemented using both FPGA and ASIC technologies in order to determine the power consumption ratio and evaluate the efficiency of the power optimization techniques such as clock gating [Amara AMARA, Philippe Royannez, VHDL for Low Power, (Chapter 11), Low Power Electronics Design, Edited by Christian Piguet, CRC Press 2005; Luca Benini, Giovanni De Micheli, Dynamic Power Management, Kluwer Academic Publishers, 1998]. We have started a study in order to compare the power consumption of two Intellectual Property (IP), a counter circuit and an image transform circuit. Both circuits have been implemented using FPGA Family circuits from ALTERA and Hardware Copy of the circuits which are close to the ASIC implementation. A full ASIC implementation using UMC 0.13 μm have be also characterized in terms of power. FPGA power consumption estimation flow is based on ALTERA tools (QuartusII) that provide accurate overall power consumption for a set of input stimuli, on various targets: FPGA families and Hardware Copy. ASIC power consumption estimation flow is based on Synopsys Power tools.

Design and Implementation of 160×192 Pixel Array Capacitive-Type Fingerprint Sensor

The application specific integrated circuit implementation of a capacitive fingerprint sensor system-on-chip (SOC), which embeds a 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of 160 × 192 array cells with a sensor detection circuit and an embedded 32-bit reduced instruction set computer (RISC) microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 80% more than conventional circuits and minimizes an electrostatic discharge influence by applying an effective isolation structure. The 32-bit RISC microcontroller is embedded by a latch base for low power and low complexity. The test chip was fabricated on a 0.35 μm standard complementary metal oxide semiconductor 1-poly 4-metal process.

Implementing an OFDM receiver on the RaPiD reconfigurable architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications that require a combination of high performance, low cost, and flexibility. Unfortunately, the use of FPGAs in mobile embedded systems platforms is hampered by the very large overhead of FPGA-based architectures. Coarse-grained configurable architectures can reduce this overhead substantially by taking advantage of the application domain to specialize the reconfigurable architecture via coarse-grained components and interconnects. This paper presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, DSP, FPGA, and coarse-grained reconfigurable architectures. RaPiD is a coarse-grained reconfigurable architecture specialized to the domain of signal and image processing. The RaPiD architecture provides a reconfigurable pipelined datapath controlled by efficient reconfigurable control logic: We have implemented the computationally intensive parts of an OFDM receiver on the RaPiD architecture and have developed careful estimates of corresponding implementations in representative ASIC, DSP and FPGA technology. Our results show that, for this application, RaPiD fills the cost/performance gap between programmable DSP and ASIC architectures, achieving a factor of 6 better than a DSP implementation but a factor of 6 less than an ASIC implementation.

Smart sensor for operational load measurement

Operation load measurement is an important technique enabling machine health monitoring and fault localization; however, direct measurement is usually difficult or impossible. The paper deals with the development of a smart sensor, which estimates the load based on structure response. In case studies, a hardware neural network was used to obtain the load course from structure vibrations - shaker-excited in a steel frame, and arising during landing in a landing gear of an airplane. The paper describes the prototype of a smart sensor, and design and implementation of load identification algorithm. For monitoring purposes, signal processing had to be done in real-time; additionally the highest possible integration level is desired, and thus a field programmable gate array (FPGA) chip was selected as the hardware platform for load estimation. The methodology of signal processing algorithms, implementation in application-specific integrated circuit (ASIC)/FPGA was developed, which allows for automation of the most time-consuming and error-prone tasks. Moreover, the same code, being the starting point for hardware synthesis, can be used in a Matlab/Simulink environment, enabling high-level system simulation and algorithm verification. Details of the procedure are presented, along with the tools used and results obtained during its realization. Performance of the smart sensor during experiment is analysed and, finally, conclusions are shown.

An application specific integrated circuit implementation of a digital beam‐forming multibeam antenna

A digital beam-forming antenna (DBF antenna) used for mobile wireless communications has drawn considerable attention in conjunction with device technology advances. Effective use of the frequency spectrum by means of multibeam antennas and adaptive antennas for mobile communications has also been discussed. With regard to DBF antennas, an offline trial process by means of a workstation and trial fabrication of a general-purpose DSP have been reported. However, to satisfy the high functionality and high-speed operation required for a DBF antenna, an application specific integrated circuit (ASIC) for the digital signal processing section must be realized. The ASIC described here is configured from a digital signal processor that uses a gate array called an FPGA, which can be developed by the user. The gate size necessary for circuit configuration obtained by a trial fabrication is explained and performance for a one-chip ASIC realized with a similar design is discussed. Experimental results are shown for real-time multibeam forming in a large anechoic chamber using the trial system. Confirmation of automatic tracking by means of maximum received beam selection is also shown. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80 (2):100–111, 1997

A novel ASIC design approach based on a new machine paradigm

A novel design methodology for rapid implementation of cheap high-performance ASICs (application-specific integrated circuits) is introduced. The method derives from high-level algorithm specifications or from high-level source programs not only the target hardware, but (in contrast to silicon compilers) also the machine code to run it. The method is based on a novel sequential machine paradigm where execution is used (being orders of magnitude more efficient) instead of simulation and where programmers may do the design job, rather than real hardware designers. It is shown that, for a very large class of commercially important algorithms (DSP, graphics, image processing and many others), this paradigm is orders of magnitude more efficient that the von Neumann paradigm. Compared to von-Neumann-based implementations, acceleration factors of up to more than 2000 have been obtained experimentally. The performance of ASICs obtained by this methodology is mostly competitive with ASIC designs obtained in the much slower and much more expensive traditional way. As a by-product the new methodology also supports the automatic generation of universal accelerators for coprocessor use in workstations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>