Application Specific Instruction Set Processor Research Articles

A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors

Application-Specific Instruction set Processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration, for example, automatic custom instruction identification and synthesis, limited on-chip data storage elements including the register file and data cache have become a potential performance bottleneck. For custom instructions that have more inputs and/or outputs than the generic register file I/O ports, custom registers are added in ASIPs to satisfy the need of additional inputs and outputs, and traditionally they are used only by custom instructions. In this article, we propose a hardware/software cooperative approach with a linear scan register allocation algorithm, which allows base instructions to utilize the existing custom registers in ASIPs for eliminating register spills of the program. The data traffic between the base processor and off-chip memory can be replaced with energy-efficient on-chip communications between the processor core and custom hardware extensions. Our experimental results demonstrate that a significant performance gain can be achieved, orthogonal to improvements by other techniques in ASIP design.

A Framework For Performance Evaluation Of ASIPs in Network-Based IDS

Nowadays efficient usage of high-tech security tools and appliances is considered as an important criterion for security improvement of computer networks. Based on this assumption, Intrusion Detection and Prevention Systems (IDPS) have key role for applying the defense in depth strategy. In this situation, by increasing network bandwidth in addition to increasing number of threats, Network-based IDPSes have been faced with performance challenge for processing of huge traffic in the networks. A general solution for this bottleneck is exploitation of efficient hardware architectures for performance improvement of IDPS. In this paper a framework for analysis and performance evaluation of application specific instruction set processors is presented for usage in application of attack detection in Networkbased Intrusion Detection Systems(NIDS). By running this framework as a security application on V850, OR1K, MIPS32, ARM7TDMI and PowerPC32 microprocessors, their performance has been evaluated and analyzed. For performance improvement, the compiler optimization levels are employed and at the end; base on O2 optimization level a new combination of optimization flags is presented. The experiments show that the framework results 18.10% performance improvements for pattern matching on ARM7TDMI microprocessors.

Hardware reuse in modern application-specific processors and accelerators

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor

An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications. An ASIP exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. ASIP Design Space Exploration can be carried out by one of the two popular available techniques as Simulator or Scheduler based approach. This paper is an attempt to survey and compare both the mentioned techniques of design space exploration of ASIP. A list of explored design space parameters using simulator based approach is included in this paper. This paper also highlights few potential parameters which can be explored using the scheduler based approach.

Loop Acceleration Exploration for ASIP Architecture

Design space exploration is a delicate process whose success lays on the designers' shoulders. It is often based on a trial-and-error approach. Some basic metrics can be used to guide this process. In this paper, we explore accelerating loops from C-based specifications. We built a framework in which a design style, such as software-oriented or application-specific instruction-set processor (ASIP)-oriented design, can be specified. We also propose an exploration process that allows targeting the main aspects that limit acceleration and the actions that can be made to improve it. The process is based on new loop-oriented metrics that provide insight in key design issues. They help to determine which aspects of the design between data accesses and arithmetic logic unit (ALU)/control operations limit or allow leveraging loop acceleration opportunities. We profile some benchmarks from the signal and image processing fields, such as the Turbo Decoder and the JPEG algorithms, to illustrate how loop-oriented metrics help to point out aspects that limit or improve loop acceleration. The loop acceleration process was also used to explore design architectures that can leverage, as much as possible, the loop acceleration opportunities of the sum of absolute differences (SAD) algorithm.

Embedded reconfigurable synchronization & acquisition ASIP for a multi-standard OFDM receiver

Embedded reconfigurable architectures are currently attracting increasing attention in the wireless communications industry due to the escalating number of wireless standards in today's market. Application specific instruction-set processors (ASIPs) present a reconfigurable solution that offers a compromise between programmability and low power consumption. In this article, the design and implementation of an embedded synchronization and acquisition ASIP for OFDM based systems is proposed. The engine architecture is presented and the programming model is explained in details. The proposed engine is scalable and it can be configured to support a multitude of synchronization algorithms and OFDM standards. While applicable to many OFDM systems, the proposed architecture was successfully verified on long term evolution (LTE Rel. 8) and WiMAX 802.16e systems. A partial list of synchronization and acquisition algorithms are tested on the engine for the two standards, and the results highlight the capabilities of the engine. The processor has been synthesized with 0.18μ m standard cell CMOS library. It is estimated to occupy 1.1 mm2 and the projected power consumption is 7.9mW at 120 MHz, which meets the speed requirements of the tested standards. More results are included within the article.

Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing

Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.

Automatic generation of compiler backends

Application-specific instruction set processors have proven successful in meeting the various design constraints of modern embedded systems and often provide the only viable trade-off between computing power and opposing metrics such as power consumption. A promising approach to facilitate the exploration of processor design alternatives are processor description languages, which capture the instruction set and hardware organization of a processor. With the use of those processor models, various design tasks, for example, the adaption of software development tools, the generation of hardware models, and various verification tasks, can be automatized. These languages thus allow effective shortening of development turnaround times. In this work, the novel xADL language is presented, which, in contrast to most contemporary processor description languages, focuses on a structural modeling of the processor's hardware organization. However, a behavioral model of the instruction set is automatically derived using instruction set extraction. This provides a tight coupling between the structural hardware view and the instruction set view of the processor and reduces the complexity of processor models in comparison with existing languages. The feasibility of our approach is demonstrated by a compiler backend generator based on tree pattern matching. An important property of our generator is its ability to automatically verify whether the resulting compiler is complete, that is, it can process all possible input programs. The generated compilers are competitive to handcrafted production compilers, showing speedups of up to 20% for certain benchmarks. On average, moderate slowdowns between 3% and 15% have been observed for several processor models while considerable reductions in code size have been measured. Copyright © 2012 John Wiley & Sons, Ltd.

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335Mbps and 176Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring

To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18µm CMOS mixed-signal process and the chip size is 2.5×2.5mm2. Evaluation results show that the power consumption of the SoC is 93.5µW, and that it can operate the capsule for seven days with a tiny battery.

Design and Implementation of a Pipelined Instruction Decoder for an ASIP DSP

An Application Specific Instruction set Processor (ASIP), a component used in System-on-a-Chip (SoC) consists of an Instruction Set Architecture called ISA designed according to the application which will be running on the processor. This specialization of the core provides a trade-off between the flexibility of a general purpose CPU and the performance of Application Specific Integrated Circuits (ASIC). During the execution of instructions in such a processor, instruction decoding is a major task for identifying instructions and generating control signals for data-paths .In this paper, a novel Instruction decoding technique is proposed that employs pipelining along with Separated Instruction Decoding(SID) and Decoder Structure Optimization (DSO) techniques to decrease the area and power. The proposed design is implemented using Verilog HDL in Xilinx and optimization results are obtained using Cadence RC Compiler 130nm technology. The experimental results shows that there is 32% improvement in area and a 58% improvement in power compared with the conventional decoder technique. The proposed pipelining logic improves the clock period compared with the existing Instruction Decoding Unit (IDU) technique with an improved area and power performance thereby making the proposed IDU technique more efficient.

Application Source Codes Profiling for ASIP Memory Subsystem Design

Application Specific Instruction-set Processors (ASIPs) are a realistic solution for domain-specific applications. To reach optimal system-level performance, memory subsystem design is considered in the pre-architecture design stage, which narrows down the huge design space to applications of a specific domain. Source code profiling approach aims to understand the characteristics of applications to guide ASIP design. The memory profiler proposed in the paper uses dynamic profiling technique to generate memory traces, and the live intervals of memory objects are computed by load-store information. Then memory requirement diagram is plotted according to instruction counts. The minimum memory requirement of the application is acquired from the diagram and guides the design of memory subsystem. The profiler is tested using a computing kernel, and the memory subsystem design suggestions are given according to the profiling results.

Enabling Fast ASIP Design Space Exploration: An FPGA‐Based Runtime Reconfigurable Prototyper

Application Specific Instruction‐set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA‐based emulators have recently been proposed as an alternative to pure software cycle‐accurate simulator. However, the advantages of on‐hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software‐driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M‐JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity‐based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India

Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

Augmenting DR-ASIP flexibility through multi-mode custom instructions

This paper introduces a simple method called multimode custom instructions, which aims at reducing the power consumption of the register file of tightly coupled dynamically reconfigurable application specific instruction set processors (DR-ASIPs). To this end, it proposes to divide custom instructions into two sets depending on criteria related to their size, distribution and reuse rate. Performance is measured on a RISC DR-ASIP with a subset of MiBench using an original automatic custom instruction generator from assembly based on the dancing link algorithm. The results show that this method makes it possible to drop the accesses to the register file made by CIs by up to 47 % with no performance hit, and to reduce the use of the context memory by up to 40 % compared to a reference architecture.

An application specific instruction set processor based implementation for signal detection in multiple antenna systems

In comparison to single antenna systems, a wireless multiple-input multiple-output (MIMO) system provides higher throughput at no additional cost of bandwidth, but the high complexity of the detection algorithms poses a major challenge to the hardware implementation. Maximum likelihood (ML) MIMO detection guarantees optimal performance but implies huge processing complexity, which makes acceptable this approach only when the number of transmitting antennas is low and the adopted modulation scheme has a small cardinality. Sphere decoding (SD) is an efficient method that significantly reduces the average processing complexity with no performance penalty.Most of known sphere decoders have been implemented as application specific integrated circuits (ASICs), but the need for high degree of flexibility in MIMO detection makes interesting also application specific instruction set processor (ASIP) implementations. A single programmable ASIP can hardly reach the same processing speed as a fully dedicated ASIC; thus, parallel architectures with multiple concurrent ASIPs must be conceived to guarantee sufficient data throughput.The objective of this paper is to present a new ASIP-based implementation for the detection of MIMO signals. The processor supports multiple lattice modulation schemes (up to 64-QAM) and up to four transmitting antennas and it is able to run both ML and close to ML algorithms. A parallel architecture has been also designed with multiple ASIPs, which concurrently execute the detection algorithm on received symbols, a central unit acting as task scheduler, and a buffer for the compensation of non constant throughput. A dedicated bus handles the communication among allocated units. Each ASIP occupies a silicon area of 0.093mm2 and runs at 400MHz when implemented on a 90nm CMOS technology. Achievable throughput depends on the adopted MIMO system and on the number of allocated ASIPs: a detector with 10ASIPs programmed to run ML detection on a 4×4 MIMO system with 64-QAM modulation offers a throughput of 78Mbps at signal-to-noise ratio SNR=18dB.

Encoding Custom Instruction Generation as Satisfiability Problem

The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefore, we present in this paper a propositional satisfiability approach to efficiently identify the custom instructions which contain a large number of valid nodes. Our approach is different substantially from the previous works where it uses an edge classification method to reduce the search space for convexity checking. The experiment results show that our method can, in a matter of few seconds, identify a set of custom instructions that speed up the application to a few times faster.

A retargetable framework for compiler/architecture co-development

Compiler-in-the-Loop (CiL) architecture exploration is widely accepted as being the right track for fast development of Application Specific Instruction-set Processors (ASIP). In this context, both, automatic application-specific Instruction Set Extension (ISE) and code generation by a compiler have received huge attention in the past. Together, both techniques enable processor designers to quickly adapt a processor's Instruction Set Architecture (ISA) to the needs of a certain set of applications and to provide an appropriate high-level programming model. This manuscript presents a tool flow for identification and utilization of Custom Instructions (CIs) during architecture exploration in an automated fashion. By embedding this tool flow in an industry-proven architecture exploration framework, a methodology for simultaneous compiler/architecture co-exploration is derived. The advantage of the presented tool flow lies in its ability to develop a reusable ISA and an appropriate compiler for a set of applications and therefore to support the design of programmable architectures. In addition, ASIP architecture exploration is effectively improved since time consuming application analysis and compiler retargeting is automated. Through compilation and simulation of several benchmarks in accordance to extended ISAs, reliable feedback on speedup, code size and usability of identified CIs is provided. Furthermore, results on area consumption for extended ISAs are presented in order to compare the obtained speedup with the invested hardware effort of new CIs.

Architectural Frameworks for Security and Reliability of MPSoCs

Multiprocessor system-on-chip (MPSoC) architectures are increasingly used in modern embedded systems. MPSoCs are used for confidential and critical applications and hence need strong security and reliability features. Software attacks exploit vulnerabilities in the software on MPSoCs. In this paper we propose two MPSoC architectural frameworks, tCUFFS and iCUFFS, for an Application Specific Instruction set Processor (ASIP) design. Both tCUFFS and iCUFFS employ a dedicated security processor for detecting software attacks. iCUFFS relies on the exact number of instructions in the basic block to determine an attack and tCUFFS relies on time-frame based measures. In addition to software attacks, reliability concerns of bit flip errors in the control flow instructions (CFIs) are also addressed. Additional method is proposed to the iCUFFS framework to ensure reliable inter-processor communication. The results for the implementation on Xtensa processor from Tensilica showed, worst case runtime penalty of 38% for tCUFFS and 44% for iCUFFS, and worst case area overhead of 33% for tCUFFS and 40% for iCUFFS. The existing iCUFFS framework was able to detect approximately 70% of bit flip errors in the CFIs. The modified iCUFFS framework proposed for reliable inter-processor communication was at most 4% slower than the existing iCUFFS framework.

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler

Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, the authors highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, the effects of OSIP and the communication architecture are investigated jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.