Abstract
Application Specific Instruction‐set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA‐based emulators have recently been proposed as an alternative to pure software cycle‐accurate simulator. However, the advantages of on‐hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software‐driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M‐JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity‐based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.
Highlights
A common feature of modern embedded systems is the need for highly optimized application-specific processing elements
The industrial methodology supports full extensibility of the instruction set through the definition of custom instructions, for the scope of this work, this possibility is not taken into account
We showed how different VLIW Application-specific instruction-set processors (ASIPs) architectures could be emulated onhardware by mapping them via software on a larger worst case configuration
Summary
A common feature of modern embedded systems is the need for highly optimized application-specific processing elements. Application-specific instruction-set processors (ASIPs) are often the only solution to the required functional and physical constraints able to provide, at the same time, high flexibility and programmability. Along with the classical characterization of hardware modules and applications with classic functional metrics (i.e., execution time, cache performance, and resource congestion), there is increasing interest in obtaining early estimations of physical metrics, such as area occupation and power/energy consumption. For all these requirements, hardware-based emulation techniques have been proposed as an alternative, more scalable, solution to cycle-accurate software-based simulation approach
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