Abstract
Embedded reconfigurable architectures are currently attracting increasing attention in the wireless communications industry due to the escalating number of wireless standards in today's market. Application specific instruction-set processors (ASIPs) present a reconfigurable solution that offers a compromise between programmability and low power consumption. In this article, the design and implementation of an embedded synchronization and acquisition ASIP for OFDM based systems is proposed. The engine architecture is presented and the programming model is explained in details. The proposed engine is scalable and it can be configured to support a multitude of synchronization algorithms and OFDM standards. While applicable to many OFDM systems, the proposed architecture was successfully verified on long term evolution (LTE Rel. 8) and WiMAX 802.16e systems. A partial list of synchronization and acquisition algorithms are tested on the engine for the two standards, and the results highlight the capabilities of the engine. The processor has been synthesized with 0.18μ m standard cell CMOS library. It is estimated to occupy 1.1 mm2 and the projected power consumption is 7.9mW at 120 MHz, which meets the speed requirements of the tested standards. More results are included within the article.
Highlights
Contemporary wireless standards allow for the radio to have connectivity with more than one technology at the same time
The results show that the hardware multiplexing in this Application specific instruction-set processors (ASIPs) solution reaches a smaller implementation area than the solution of multiple dedicated implementations
The processor can support a multitude of orthogonal frequency division multiplexing (OFDM)-based standards
Summary
Contemporary wireless standards allow for the radio to have connectivity with more than one technology at the same time. There is a need to design, and efficiently implement high accuracy synchronization algorithms using embedded reconfigurable engines that can support the increasing number of OFDM-based standards. Configurable radio architectures that can support multiple standards were proposed in [9,10], where the engine core consists of an array of reconfigurable units. The total number of time samples in one OFDM symbol is Ns = N + Ng. The received signal, when the transmitted signal passes through a channel with an impulse response h(t) is r(t) = hi(t)s(t − τi) + n(t). Tracking the variations of the CFO and SCFO is critical in OFDM systems due to their sensitivity to frequency offsets. Four processes are performed in this phase: symbol timing (frame boundary detection), initial fractional CFO (FCFO) estimation, cell-search (CS) and ICFO estimation. Optimized architectures that fulfill the needs of the synchronization sub-system with a high degree of configurability will have the advantage in terms of area and power
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