FIJI: Fault InJection Instrumenter

Fault injection is a critical technique for assessing the reliability of field programmable gate array (FPGA)-based embedded systems, particularly in radiation-prone and safety-critical applications. Conventional fault injection methods, such as bit upset fault injection testing (BUFIT), single critical fault injection testing (SCFIT), and dynamic partial reconfiguration (DPR), suffer from high resource overhead, slow injection speeds, and limited adaptability, making them inadequate for real-time fault resilience evaluation. This article introduces the dynamic adaptive fault injection server (DA-FIS), a high-speed, scalable, and resource-efficient fault injection framework designed to overcome these limitations. Unlike traditional methods, DA-FIS employs a configurable LFSR-based fault generator that enables adaptive and real-time fault injection based on workload sensitivity and system conditions. The proposed framework integrates masking logic and dynamic propagation tracking, allowing precise injection of single-event upsets (SEUs) and multiple-bit upsets (MBUs) into FPGA configuration memory and logic without disturbing non-targeted regions. DA-FIS is implemented on the Xilinx Zynq-7000 FPGA and evaluated across multiple benchmark workloads, including the Bubble Sort algorithm, 4-bit adder, 4-bit multiplier, and counter-based logic circuits. Experimental results demonstrate that DA-FIS achieves a fault injection rate of 111.1 faults per second, outperforming BUFIT (53.4 faults/s), SCFIT (27 faults/s), and DPR (18.5 faults/s), with 30% lower FPGA resource overhead compared to SCFIT. The adaptive architecture ensures seamless scalability across different FPGA platforms, making it suitable for space electronics, automotive safety systems, and high-performance computing. Additionally, DA-FIS supports real-time error model adjustments, enabling researchers to analyze fault propagation, error correction strategies, and security vulnerabilities in FPGA-based architectures. This work establishes DA-FIS as a superior fault injection framework, offering high-speed, precision-controlled fault testing while maintaining minimal FPGA overhead and enhanced scalability. Future research will explore machine learning-assisted fault modeling and self-healing FPGA architectures to further enhance FPGA fault resilience in safety-critical and autonomous systems.

Challenges related to verification and validation (VV) of FPGA-based safety critical I&C systems (FICS) are analyzed. One of the mandatory techniques applied in process of VV and certification to requirements of IEC 61508 according with safety integrity level (SIL) is the fault insertion or injection testing (FIT). Specific features of FICS SIL-certification and FIT are described. Concept of FIT-ability, some theoretical issues and algorithm of the optimal FIT procedure taking into account different points and means of fault injection are suggested. The developed technique and tool VTP has been applied to verify modules of FPGA-based platform RadICS during SIL-certification.

Soft-core processors and complex Field Pro-grammable Gate Array (FPGA) designs are described as an algorithmic manner, i.e. behavioural abstraction level in Hard-ware Description Languages (HDL). Lower abstraction levels add complexity and delays in the design cycle as well as in the fault injection approach. Therefore, fault simulation/emulation techniques are demanded to develop an approach for testing of design and to evaluate dependability analysis of FPGA designs at this abstraction level. Broadly, the fault injection techniques for FPGA-based designs at the HDL code level are categorised into emulation and simulation-based techniques. This work is an extension of our previous methodologies developed for FPGA designs written at data-flow and gate abstraction levels under the proposed RASP-FIT tool. These methodologies include fault injection by code parsing of the SUT, test approach for finding the test vectors using dynamic and static compaction techniques, fault coverage, and compaction ratio directly at the code level of the design. In this paper, we described the proposed approaches briefly, and the enhancement of a Verilog code modifier for the behavioural designs is presented in detail.

Modern large-scale service systems are usually deployed with redundant components to ensure high dependability in distributed and volatile environments. Fault Injection Testing (FIT) is a popular technique for testing such systems, while the application of FIT to validating the correctness of redundant components remains a challenging task, especially when the system's structural information is unavailable when testing starts. In this study, we refer to a minimum set of faults that, when injected, will cut off all execution paths in a service system as a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fault-tolerance bottleneck</i> , and we propose a novel Fault-tolerance Bottleneck driven Fault Injection (FBFI) approach to the exploration and validation of redundant components without prior knowledge of the system's business structure. The core idea of FBFI is to iteratively infer and inject bottlenecks of the business structure constructed so far. In this way, FBFI is able to discover and test redundant components by repeatedly triggering new system behaviors. The effectiveness and efficiency of FBFI is evaluated using two microservice benchmark systems with different deployment scales. The results reveal that FBFI is more practical and cost-effective than random and lineage-driven FIT approaches in testing service systems of high redundancy levels.

This paper presents an approach for conformance testing and fault injection of distributed systems supported by a tool named FSoFIST (Ferry-clip with Software Fault Injection Support Tool). The approach extends the ferry-clip concept to cope with fault injection. The ferry-clip concept was aimed at providing a highly modular, flexible and configurable architecture for protocol conformance testing. Due to these qualities, this architecture can be used for testing different protocol implementations with reduced effort. The work presents the design issues employed to achieve the ferry-injection architecture and describe the components of the proposed architecture. The capabilities of the approach are demonstrated in a case study used to validate the FSoFIST tool.

List of Figures 5.3 Example LUT descriptors extracted from the netlist in Vivado . . 93 5.4 Example of bit-accurate LUT mapping . . . . . . . . . . . . . . . . 94 5

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest parts of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Cooperation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject faults at different levels of abstraction. The experimental results show that this approach can significantly reduce the time needed for executing fault injection campaigns.

With the recent popularity of model-based design and verification (MBDE), fault injection testing at the functional model level is gaining significant interest. The reason for this interest is it aids in detecting design errors and incorrect requirements on fault detection and tolerance features, very early in the development lifecycle. This is evidenced by the fact that functional safety standards like IEC 61508 and ISO 26262 identify fault injection testing as a highly recommended technique for SIL-3 and SIL-4. The main challenges to date with model-based fault injection are lack of completeness in the fault injection space, semi-manual integration and insertion of fault injection modules into the models and manual identification of fault activation conditions. The work presented in this paper describes a novel model-based fault injection technique that is property-based and applies formal model checking verification methods at the functional model level of design thereby guaranteeing a near-exhaustive state, input and fault space coverage. This method also introduces the usage of properties and model checking capabilities to automate the identification of fault activation conditions for all the faults within the fault space. We describe the workflow and implementation of the property-based Fault injection using Simulink Design Verifier and its application on the functional model of a representative safety-critical system.

Web service orchestrations are widely adopted solution for development of loosely-coupled distributed applications. In addition to traditional defects causing failures in the software systems, their quality is also affected by additional problems such as network latency, interface inconsistency or communication issues. Тhe fault injection testing is useful for validation the behavior of the web service orchestrations when such problems occur. That is why we propose an approach based on fault injection technique for generation and execution of fault tolerance test cases. The approach is automated through implementation of two software tools for fault injection and test case generation and execution Those tools are integrated in a common testing framework, called TASSA, presented in this paper. They are validated on a case study through simulation of different type of failures and fault tolerance testing of a web service orchestration.

The rapid advancement of AI has led to its integration into various areas, especially with Large Language Models (LLMs) significantly enhancing capabilities in Artificial Intelligence Generated Content (AIGC). However, the complexity of AI systems has also exposed their vulnerabilities, necessitating robust methods for Failure Analysis (FA) and Fault Injection (FI) to ensure resilience and reliability. Despite the importance of these techniques, there lacks a comprehensive review of FA and FI methodologies in AI systems. This study fills this gap by presenting a detailed survey of existing FA and FI approaches across six layers of AI systems. We systematically analyze 142 studies to answer three research questions including (1) what are the prevalent failures in AI systems, (2) what types of faults can current FI tools simulate, (3) what gaps exist between the simulated faults and real-world failures. Our findings reveal a taxonomy of AI system failures, assess the capabilities of existing FI tools, and highlight discrepancies between real-world and simulated failures. Moreover, this survey contributes to the field by providing a framework for fault diagnosis, evaluating the state-of-the-art in FI, and identifying areas for improvement in FI techniques to enhance the resilience of AI systems.

Fault injection technology is an important part of embedded system testing, it can simulate the software anomaly and hardware failure in the system. Fault injection testing has become a part of many device tests. This paper provides a hardware design based on ZYNQ 8-channel input-output module with fault injection. Each channel can support analog signal acquisition, analog signal output, and fault injection function for analog signal output. The channel type and fault injection type are determined through software configuration, which greatly improves the flexibility of the device.

The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A Light-Weight Fault Injection Approach to Test Automated Production System PLC Software in Industrial Practice

Today, Many industries are studying methods that enhance and measure dependability. Dependability measurement methods use fault injection to monitor the state of a system. A fault/error that occurs in an unexpected situation, giving rise to an extreme status, can be inspected. To obtain high Automotive Safety Integrity Level (ASIL) in automotive safety standard (ISO 26262), any system must be tested using fault injection technique. NASA standard (8719.13B) also recommends the fault injection test. In contrast, the medical device safety standard (ISO 14971) does not mention the fault injection test. In this paper, we compare the difference between two standards and introduce a method of fault injection in medical device.