Analog Circuit Applications Research Articles

0.5 V bulk ‐ driven CMOS fully differential current feedback operational amplifier

This study presents a new low-voltage fully differential current feedback operational amplifier for ultra-low-voltage and low-power analogue circuit applications. A bulk-driven technique is used to reduce the supply voltage requirement and also provides a rail-to-rail input voltage common-mode swing. The proposed circuit has been simulated using a TSMC 0.18 µm n-well CMOS technology with a 0.5 V supply voltage. Simulation results show that the static power consumption of the proposed circuit is 4.7 µW. The proposed circuit has been used to realise fully differential integrators and fully low-pass/band-pass second-order filters to express the performance of the new circuit.

Monolayer Graphene Field Effect Transistor-Based Operational Amplifier

Graphene Field Effect Transistor (GFET) is a promising candidate for future high performance applications in the beyond CMOS roadmap for analog circuit applications. This paper presents a Verilog-A implementation of a monolayer graphene field-effect transistor (mGFET) model. The study of characteristic curves is carried out using advanced design system (ADS) tools. Validation of the model through comparison with measurements from the characteristic curves is carried out using Silvaco TCAD tools. Finally, the mGFET is used to design a GFET-based operational amplifier (Op-Amp). The GFET Op-Amp performances are tuned in term of the graphene channel length in order to obtain a reasonable gain and bandwidth. The main characteristics of the Op-Amp performance are compared with 0.18[Formula: see text][Formula: see text]m CMOS technology.

Modeling technology of InP heterojunction bipolar transistor for THz integrated circuit

AbstractIndium phosphide (InP)‐based transistors play an important role in high‐speed circuit and high‐frequency analog circuit applications. Over the past few decades, terahertz heterojunction bipolar transistor (HBT) is increasingly developed. As a result, many reports of HBTs operating at terahertz region have flourished. Since the high‐frequency circuit design faces the challenge from the lack of precise transistor models, this paper reviews the development of high‐frequency modeling technologies of InP HBT at terahertz region. Processes in the development of small‐signal models at terahertz frequencies, precise parasitic parameters extraction method, improvements in measurement, and the de‐embedding technologies open up more opportunities for precise representation of InP HBTs. Finally, some excellent terahertz circuits based on InP HBT are reviewed.

Abnormal Capacitance Increasing at Elevated Temperature in Tantalum Capacitors with PEDOT:PSS Electrodes

Due to the importance of capacitance temperature stability in precise analog circuit applications, capacitance instability at elevated temperature of 125°C was investigated in tantalum capacitors with PEDOT:PSS counter electrodes. Capacitance-voltage measurement supposed that residual ions in the PEDOT:PSS dispersion caused an accumulation of charges at the dielectric-cathode interface which contributed to an increase in the dielectric constant and resulted in the capacitance increasing at high temperature. Based on the hypothesis, water wash process was applied and capacitance dropped significantly at high temperature. This study shows that an additional water wash process is necessary to improve the capacitance temperature stability after each dispersion dip step.

Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications

Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications

Analog Circuit Applications Based on Ambipolar Graphene/MoTe2 Vertical Transistors

AbstractThe current integrated circuit technology based on conventional metal–oxide–semiconductor field‐effect transistor (MOSFET) is approaching the limit of miniaturization with increasing demand on energy. Several analog circuit applications based on graphene FETs have been demonstrated with less components comparing to the conventional technology. However, low on/off current ratio caused by the semimetal nature of graphene has severely hindered its practical applications. Here, a graphene/molybdenum ditelluride (MoTe2) van der Waals (vdW) vertical transistor with V‐shaped ambipolar field‐effect transfer characteristics to overcome this challenge is reported. Investigations on temperature dependence of transport properties reveal that gate‐tunable asymmetric barriers of the devices are account for the ambipolar behaviors. Furthermore, to demonstrate the analog circuit applications of such vdW vertical transistors, output polarity controllable amplifier and frequency doubler are successfully realized. These results enable vdW heterojunction‐based electronic devices to open up new possibilities for wide perspective in telecommunication field.

14-nm FinFET Technology for Analog and RF Applications

This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a ${F}_{t}/{F}_{\text {max}}$ of 314/180 GHz and 285/140 GHz for ${N}$ and PFinFET device, respectively. The double-side gate contact structure with contact on either end of active gate enhances the peak ${F}_{\text {max}}$ performance to 227 and 195 GHz for both ${N}$ and PFinFET devices, respectively. A significant boost in the PFinFET RF performance is observed compared to 28-nm planar PFET, which is attributed to the source/drain SiGe epitaxy stressor that results in higher hole carrier mobility. On the other hand, the thin channel body of FinFET structure facilitates a better electrostatic control of gate over the channel region and hence suppresses short channel effects including the drain-induced barrier lowering. Consequently, a significantly higher self-gain ( ${G}_{m}/{G}_{\text {ds}})~40$ and 34 for both NFinFET and PFinFET is achieved. In addition, N/PFinFETs demonstrate superior 1/f noise of 17/35 fV $^{2}\mu \text{m}^{2}$ /Hz at 1 kHz compared to 171/106 fV $^{\mathrm {\mathbf {2}}}\mu \text{m}^{2}$ /Hz of 28-nm planar N/PFETs. To extend the low-voltage operation and power saving of FinFET RF platform, ultralow ${V}_{t}$ N/PFinFETs in the range of 50 mV ${V}_{t}\text{s}$ are also developed. Furthermore, a deep n-well process is added to the platform to provide device and circuit isolation from substrate and supply noise, while realizing the creation of new devices such as vertical NPN, PCAP, and high breakdown voltage deep n-well junction diodes. Overall, a superior ${F}_{t}/{F}_{\textsf {max}}$ , high self-gain, low 1/f noise, and robust substrate isolation characteristics extend the capability of this new 14-nm FinFET technology to the analog and RF circuit applications.

Intrinsic mechanism in nonvolatile polycrystalline zirconium oxide sandwiched structure

Based on the ZrO2 core layer, two kinds of resistive memory cells with Ag/ZrO2/Ag and Ag/ZrO2/ITO sandwiched structures were prepared by a magnetron sputtering system. After thermal treatment, the sample cells show the stable bipolar resistive switching characteristics at room temperature in the current–voltage measurements. The intrinsic mechanism can be well interpreted by the space charge limited conduction effect with charged defects. Two different types of bottom electrode Ag and ITO showed different characteristics. The excellent resistive switching characteristics in the sandwiched structure with ZrO2 core layer makes it to be a promising candidate for the nonvolatile storage and programmable analog circuit applications.

Evaluation of Negative Capacitance Ferroelectric MOSFET for Analog Circuit Applications

Negative capacitance ferroelectric (FE) field-effect transistor (FeFET) is promising to address the issue of the increasing power density in digital circuit by realizing sub-60 mV/decade subthreshold swing. This inspires us to evaluate its applications in analog circuit. In this paper, the evaluation is performed based on the equivalent circuit model and through device- and circuit-level benchmarking against MOSFET counterpart. It is found that the selection of FE thickness is important to balance current amplification and saturated output characteristics. As compared with MOSFET, FeFET exhibits a larger current, transconductance, and current-to-transconductance generation efficiency. Its output resistance is smaller in the linear region and larger in the saturation region. It also has less variation in threshold voltage with temperature. When implementing FeFETs into various analog circuit applications, we find that a node capacitor could be discharged within shorter time to increase circuit speed; A better analog switch consisting of complementary FeFETs exhibits a lower and more linear on-resistance; Differential amplifier provides larger voltage amplification to small input signal; Current mirror transfers a more precise output current to the reference one.

Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET

Temperature is a thermal parameter which affects the device performance. This paper presents the impact of the temperature variation on the electrical characteristics such as tunneling width, subthreshold swing, threshold voltage, and ION/IOFF ratio of Ge/Si heterojunction Silicon on Insulator (SOI) Tunnel Field Effect Transistor (TFET) for different drain voltages. The device exhibits better performance in comparison with homojunction of the same device for different temperatures. This study reveals that OFF current of the device is independent of drain voltage variation irrespective of temperature variation. A small change in the subthreshold swing (SS) with temperature variation shows the weaker dependence of SS on temperature. The analog performance parameters such as transconductance, output transconductance, gate capacitance, and transconductance-to-drain-current ratio of the device are also examined. A small variation in analog parameters with temperature variation shows that the device could be used for the high-temperature analog circuit applications. A broad range of temperature from 200 K to 400 K has been used to analyze the performance of the device using Synopsys Technology Computer Aided Design (TCAD) simulation tool.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Development of noise model for InAsSb MOSFETs and their application in low noise amplifiers

In this paper, we develop the low frequency noise (LFN) model for symmetric double gate InAsSb channel n-MOSFETs and report noise performance of such devices as well as amplifier circuits built using them. Our noise model relies on the drain current Id which is obtained from the carrier concentration and Pao-Sah’s current formulation taking into account field dependent electron mobility and interface trapped-charge density Dit. The drain current model is calibrated with reported experimental data. The calculated values of Id and transconductance gm are utilized to find power spectral density of drain current as a function of drain and gate bias voltages, channel length, channel thickness, equivalent oxide thickness and also Dit. Moreover, we have studied the performance of low noise amplifiers (LNAs) with simultaneous noise and input matching (SNIM) topology using both InAsSb and Si channel devices, and computed the minimum noise figure and output noise power density and compared the results. Our investigation reveals that InAsSb MOSFETs exhibit better low noise performance in the strong inversion region of operation at which devices are biased to operate usually for analog circuit applications. Furthermore, the LNA with InAsSb channel MOSFET exhibits noise figure of 1.38 dB in strong inversion region enabling the amplifier suitable for many applications.

Conduction Mechanisms in Multiferroic Multilayer BaTiO3/NiFe2O4/BaTiO3 Memristors

Memristive devices and materials are extensively studied as they offer diverse properties and applications in digital, analog and bio-inspired circuits. In this paper, we present an important class of memristors, multiferroic memristors, which are composed of multiferroic multilayer BaTiO3/NiFe2O4/BaTiO3 thin films, fabricated by a spin-coating deposition technique on platinized Si wafers. This cost-effective device shows symmetric and reproducible current–voltage characteristics for the actuating voltage amplitude of ±10 V. The origin of the conduction mechanism was investigated by measuring the electrical response in different voltage and temperature conditions. The results indicate the existence of two mechanisms: thermionic emission and Fowler–Nordheim tunnelling, which alternate with actuating voltage amplitude and operating temperature.

A general memristor model and its applications in programmable analog circuits

This paper focuses on presenting a new memristor model with a general window function. Three adjustable parameters are introduced such that it is more flexible. It is seen that several well-known window functions are the special cases of the general window function. Some issues (e.g., the boundary lock and limited scalability) encountered in previously reported memristor models are thus efficiently resolved. Furthermore, fine-resolution programmable resistance is achieved by controlling the parameters of the general memristor model. The programmable analog filter and gain amplifier are finally implemented to illustrate the applications of the developed memristor model.

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling.

(Invited) Performance Limit and Potential of Layered MoTe2 Transistors

Atomically thin flaks were obtained to fabricate field-effect transistors by using mechanical exfoliation of 2H-type α-molybdenum ditelluride (MoTe2) bulk crystal grown by chemical vapor transport. Both static and dynamic charge transport of these layered transistors were systematically investigated to explore the underlying mechanism of charge transport. In the quasi-static measurements, carrier ambipolarity was observed and originated from the formation of tunable Schottky barriers at the metal/MoTe2 contacts. In the dynamic measurements, .the 1/f dependence of the noise was observed in the conducting channels in vacuum and followed the carrier number fluctuation model. Moreover, the noise spectrum in ambient conditions changed to a Lorentzian, possibly because a large number of gas molecules absorbed at the chalcogen vacancies, enhancing the trapping and emission of carriers between two discrete energy states. Using such unique layered transistors, we further realized complementary-like inverters, amplifiers and environmental sensors, demonstrating their feasibility for future digital and analog circuit applications.

Sharp Switching Characteristics of Single Electron Transistor with Discretized Charge Input

For the low-power consumption analog and digital circuit applications based on a single-electron transistor, enhancement of its switching performance is required. Our previous works analytically and numerically demonstrated that a discretized charge input device, which comprised a tunnel junction and two capacitors, improved the gain characteristics of single-electron devices. We report the design and fabrication of an aluminum-based single-electron transistor having the discretized charge input function. Flat-plate and interdigital geometries were employed for adjusting capacitances of grounded and the coupling capacitors. The sample exhibited clear switching on input-output characteristics at the finite temperature.

A 500 °C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 °C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 °C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 °C are 0.79 and 1.01 LSB, respectively, while at 500 °C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 °C and 500 °C, respectively.

State of the art of metal oxide memristor devices

AbstractMemristors are one of the emerging technologies that can potentially replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. Over the past few years, research and development mostly focused on revolutionizing the metal oxide materials, which are used as core components of the popular metal-insulator-metal memristors owing to their highly recognized resistive switching behavior. This paper outlines the recent advancements and characteristics of such memristive devices, with a special focus on (i) their established resistive switching mechanisms and (ii) the key challenges associated with their fabrication processes including the impeding criteria of material adaptation for the electrode, capping, and insulator component layers. Potential applications and an outlook into future development of metal oxide memristive devices are also outlined.

DTMOS Transistor with Self-Cascode Subcircuit for Achieving High Bandwidth in Analog Applications

work, an improved dynamic threshold MOS (DTMOS) transistor with self-cascode subcircuit has been proposed in this work. By adopting the self-cascode subcircuit, the proposed DTMOS transistor could be operated at supply voltage over 0.7V. Apart from this, simulation results for the proposed DTMOS, also demonstrate improvement in the transconductance and bandwidth by a factor of 2.31 and 1.59 respectively. Furthermore, the current driving capability of proposed DTMOS transistor has increased by a factor of 1.87. To validate the proposed concept and its applications in analog circuits, a current mirror and a differential amplifier have been designed in 180nm CMOS technology. Both circuits are able to operate at higher bandwidth as compared to their conventional counterparts. The Monte Carlo simulations reflect the robustness of the circuits to device mismatch errors. The proposed DTMOS transistor is more suitable for large signal circuits such as mixer and voltage control oscillator. Keywordsthreshold MOS transistor (DTMOS), Self-Cascode, bandwidth, transconductance, analog integrated circuits.