Analysis Of Through-silicon Vias Research Articles

Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface

In this paper, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate’s effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented, and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7 % and 4.7 % at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1 % at 8 Gb/s, verifying the low-power structure.

Low-loss through silicon Vias (TSVs) and transmission lines for 3D optoelectronic integration

The optoelectronic hybrid integration based on co-package has attracted much attention to meet the requirements of high-performance chip development and functional integration. TSVs and redistribution layers (RDLs) are of great importance for both the packaging process and the system design of 3D integration. This paper presents the measurements and analysis of TSV and RDL test structures, from DC to high frequency up to 67 GHz. TSVs and RDLs with low insertion loss up to 67 GHz are demonstrated and the impact of TSV arrangements on the transmission performance are analysed. The insertion loss of a 500 μm long coplanar waveguide (CPW) transmission line of frontside RDL (FSRDL) is 0.75 dB at 67 GHz. The insertion loss is less than 1 dB at 67 GHz for a TSV-RDL signal path with the length of 500 μm.

Transient Analysis of Through-Silicon Vias in Floating Silicon Substrate

For through-silicon vias (TSVs) in a floating silicon substrate, electric fields from signal TSVs terminate at ground TSVs instead of the substrate. The MOS capacitance of TSVs in a floating silicon substrate is quite different from that of TSVs in a well-grounded silicon substrate. Therefore, it is essential to perform transient analysis of such TSVs to facilitate designs and applications of 2.5-D and 3-D ICs. This paper presents a systematic study of time-domain responses of TSVs in a floating silicon substrate. Impacts of the floating substrate and the temperature are considered and investigated thoroughly. The equivalent circuit models are developed and applied to predict the signal propagation. The crosstalk voltages among TSVs are accurately captured and compared for different oxide charges and temperatures.

Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias

In this paper, a 3-D thermomechanical model of through-silicon vias (TSVs) has been analyzed and verified with in situ microscale strain measurements by synchrotron X-ray microdiffraction. Thereafter, a comprehensive stress/strain analysis on copper pumping and back-end-of-line (BEOL) cracking issues has been carried out. In addition, a design-of-experiments-based approach has been used to understand the effect of various parameters on copper pumping and BEOL stress. The results show that the smaller TSV diameter and thinner silicon die help reduce the copper pumping and thus mitigate BEOL stress.

Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration

Measurement-based electrical characterization of through silicon via (TSV) and redistribution layer (RDL) is of great importance for both fabrication process and system design of 3D integration. This paper presents the electrical measurements and analysis of TSV and double-sided RDL test structures, from DC to high frequency up to 40GHz. TSV shows great dependence of DC resistance and leakage current on fabrication process. An inverse V-shaped C–V curve is presented between adjacent TSVs in N-type silicon substrate, from −10V to 10V. In the high frequency characterization, two methods are proposed and applied to extract resistance and inductance of a single grounded TSV. Individual transmission loss of TSV, RDLs on top and bottom surface of silicon substrate are calculated, and corresponding circuit parameters thereof are extracted to characterize their electrical properties precisely.

Transient Analysis of TSV Equivalent Circuit Considering Nonlinear MOS Capacitance Effects

An equivalent circuit model for the transient analysis of through-silicon vias (TSV) taking into account nonlinear metal-oxide-semiconductor effects is proposed. The model takes into account the nonlinear behavior of the doped silicon substrate in presence of the electric potential difference due to the transient voltage between the TSVs. The impact of time-variant capacitance between the via and the substrate on crosstalk and signal propagation is analyzed.

Identification of Through-Silicon Via (TSV) Failure Points Using the Time Domain Reflectometry (TDR) Method

Time domain reflectometry (TDR) is applied to the failure analysis of through-silicon vias (TSVs). The reflection time of the TDR signal from test-element-group (TEG) chips with TSVs stacked on a silicon interposer is compared to the distance between the failure point and the contact pad derived from a TDR simulation value, using a model which has the same structure as the TEG chips. These results show good agreement between the simulated and the measured results.

Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

Through-silicon vias (TSVs), being one of the key enabling technologies for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and even less experimental failure analysis has been reported in the literatures.In this paper, TSV samples have been fabricated and tested under thermal-shock test from −55°C to 125°C. Various experimental techniques have been used to carry out the failure mechanism analysis. Both Cu/SiO2 interfacial separations and SiO2/Si cohesive cracking were identified at various locations along the Cu/SiO2/Si interfaces. Finite-element based fracture analysis models have also been developed to understand the interfacial/cohesive crack initiation and propagation. A centered finite difference approach (CFDA) based on Griffith’s energy balance has been developed for the axisymmetric crack propagation analysis. Also, the virtual crack closure technique (VCCT) has been applied for the axisymmetric interfacial/cohesive crack analysis. Both methods match perfectly with each other for linear elastic analysis, and agree well for elastic–plastic analysis. The fracture analysis results match the experimental observations, and also provide insight on the reason behind different failure mechanisms.

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLCG</i> ) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.

Failure Analysis and Process Improvement for Through Silicon Via Interconnects

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.