Analysis Of Parasitic Effects Research Articles

Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses

This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit&#x0027;s area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced by 66.67&#x0025; due to the crossbar&#x0027;s parasitics, non-idealities of the neuron, and memristor circuits. The memristor&#x0027;s state, either low or high resistance, significantly affects the system&#x0027;s performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 &#x00A0;<inline-formula><tex-math notation="LaTeX">$nJ$</tex-math></inline-formula>, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.

Full Custom MEMS Design: 2.5D Fabrication-Process Simulation for 3D Field-Solver-Based Circuit Extraction

Due to the lack of sophisticated component libraries for microelectromechanical systems (MEMS), highly optimized MEMS sensors are currently designed using a polygon-driven design flow. The advantage of this design flow is its accurate mechanical simulation, but it lacks a method for an efficient and accurate electrostatic analysis of parasitic effects of MEMS. In order to close this gap in the polygon-driven design flow, we present a customized electrostatic analysis flow for such MEMS devices. Our flow features a 2.5D fabrication-process simulation, which simulates the three typical MEMS fabrication steps (namely deposition of materials including topography, deep reactive-ion etching, and the release etch by vapor-phase etching) very fast and on an acceptable abstraction level. Our new 2.5D fabrication-process simulation can be combined with commercial field-solvers such as they are commonly used in the design of integrated circuits. The new process simulation enables a faster but nevertheless satisfactory analysis of the electrostatic parasitic effects, and hence simplifies the electrical optimization of MEMS.

Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO2 devices implemented in a 250-nm BiCMOS IHP technology.

Analysis of parasitic effects in carrier signal injection methods for sensorless control of PM synchronous machines

This study presents the parasitic effects on different carrier signal injection methods with alternative sensing signals for the sensorless control of permanent magnet synchronous machines (PMSMs). The different carrier injection methods are the rotating injection in the stationary reference frame with carrier current sensing and with zero-sequence carrier voltage sensing, the pulsating injection in the estimated synchronous reference frame with carrier current sensing, and pulsating injection in the anti-rotating reference frame with zero-sequence carrier voltage sensing, respectively. The parasitic effects, e.g. the magnetic saturation, inverter non-linearity, iron and PM losses, torque ripple etc. will be fully analysed and compared for these different injection methods. All the theoretical analyses are validated by either finite-element analyses or experiments on a laboratory PM machine.

Analysis of parasitic effects in triple‐well CMOS SPDT switch

A comparison between a conventional body floating single pole double throw (SPDT) CMOS switch design and a proposed switched gate floating CMOS SPDT switch design based on an analysis of parasitic effects is presented. In standard CMOS technology, the switched gate floating switch is analytically proved to have higher isolation owing to the alleviation of parasitic diode and substrate coupling effects in the operation state. The proposed switch maintains a similar insertion loss as conventional swithches while achieving an average of 6 dB isolation improvement over the operating frequency, which agrees well with the presented analysis.

Analysis of parasitic effects for pin diode SPDT switch

A comparison of insertion loss between a conventional clockwise and a proposed counter-clockwise SiGe pin diode SPDT switch based on an analysis of parasitic effects is presented. In a silicon-based process, the counter-clockwise switch is analytically demonstrated to have lower insertion loss than the clockwise switch owing to the alleviation of parasitic effects. Measurement data show good agreement with the presented analysis.

Novel fast multiline analysis of parasitic effects in CPW inductors for MMICs

The author presents a novel multiline modeling of monolithic microwave integrated circuit (MMIC) spiral inductors in coplanar waveguide (CPW) technology. Starting from transmission line parameters calculated for only single lines and pairs of lines, a distributed equivalent circuit is established for each section of multicoupled lines in the structure. It readily yields the S-parameters of the section. An adequate interconnection of sections having different topologies results in the S-matrix of the device. Our technique is wideband, fast, and fully scalable. It predicts on-line the effect of the underpass and of spurious propagation along the coplanar waveguide (CPW) grounding. It is shown that a significant frequency shift is due to the combination of those two effects. Results are validated by measurements on SOI inductors, up to the second self-resonance frequency.