Analog Circuits Research Articles

Development and characterization of log periodic feedline based filter for water leakage detection in size invariant PVC pipes

In this proposed work, water leakage detection in Polyvinyl chloride (PVC) pipes has been investigated using a ring filter connected to log-periodic feedlines (LPF). The proposed filter has a well-structured ring design to adjust the PVC pipes and operates between 0.3 GHz & 0.7 GHz. Using a signal generator & analyzer, attenuation measurements are obtained to analyze the impact of water leakage. PVC pipes with varying diameters (3 inches, 2 inches, 1.5 inches, & 1 inch) are connected with water stoppers to control the water flow during experiments. The leak is contained within a plastic tub to make measurements easier. Results show a good connection between attenuation & water level for all pipe diameters, supporting the LPF-based ring filter’s effectiveness as a leakage detector. An analogous circuit model is created to evaluate the filter’s performance further. At the same time, the resonant parameters, such as Q-factors & resonant frequencies, are retrieved from S21 magnitude measurements in the operating frequency range. The proposed methodology is shown to be accurate & reliable, offering significant potential for water leakage detection in PVC pipe systems. By accurately detecting water leakage, this technology enables prompt repairs, reducing water loss & associated costs, enhancing water infrastructure, and promoting sustainable water management.

Understanding Chua system from the perspective of Duffing

The generation methods and structure of the multi-scroll chaotic attractors in both the Chua system and the Duffing equation exhibit remarkable similarities, suggesting a potential relationship between these two systems. Specifically, the Chua system can be transformed into a Duffing-like equation. In this transformation, the second equation of the Chua system forms the main body of the Duffing equation, while the first and third equations contribute to forming potential wells. Consequently, parameters in the Chua system possess physical meanings corresponding to those in the Duffing equation, enabling us to control the Chua system as if it is a Duffing equation. By adjusting various factors such as damping coefficient, potential difference among potential wells, the shape of the potential wells, asymmetric bias, external driving force and oscillation characteristics of potential wells within Chua system framework, we can successfully obtain controllable multi-scroll chaotic attractors. The Multisim simulation circuit and analog circuit experiments have confirmed the results.

Fault Simulation for Dynamic Failures in Analog and Mixed-Signal Circuits

Fault Simulation for Dynamic Failures in Analog and Mixed-Signal Circuits

Real-Time Method and Implementation of Head-Wave Extraction for Ultrasonic Imaging While Drilling

Extracting head waves and subsequently uploading their results from the downhole to the surface system in real time could improve the real-time guidance of ultrasonic imaging logging while drilling (UILWD) for drilling operations. To realize the downhole real-time extraction of head waves in this logging, three aspects were explored in this study. First, an improved energy ratio head-wave arrival extraction algorithm based on the weighting coefficients and characteristic functions, along with an amplitude detection method relying on peak-to-peak values, was proposed. Second, an echo reception pre-processing analog circuit and a digital signal processing circuit based on FPGA were designed. A pipeline algorithm was developed in FPGA to extract the arrival time and amplitude of the head wave. Finally, software simulations, laboratory tests, and field experiments related to this method were conducted. Our results showed that the real-time head-wave extraction method demonstrated a strong anti-noise ability in real time. The maximum relative error of the arrival time was less than 5%. The relative error of the amplitude was acceptable, and 90% of this value was within 5%. Through the measurement, the time of processing a single-channel waveform by a downhole algorithm was less than 15 ms, thus meeting the requirements for the real-time processing of downholes.

Dynamics modeling of a memristor-based Rucklidge chaotic system: Multistability, offset boosting control and FPGA implementation

The complex dynamics greatly contributes to the application of chaos, especially the memristor chaotic systems that have emerged very recently. In this paper, a novel four-dimensional continuous chaotic system is developed by introducing a generalized memristor model into the classical Rucklidge system, and the rich dynamical traits are confirmed by theories and numerical simulations. System Hamilton energy is deduced and analyzed to expose the underlying energy evolution and chaos mechanism. And then, realizing the offset boosting control of the system promotes its engineering applications. Numerical simulations verify that the offset boosting controller can directly change the polarity of the chaotic signal. Specifically, bifurcation diagram, Lyapunov spectra, system complexity evolution diagram and dynamic evolution map are adopted to expound the rich dynamics. Meanwhile, the extreme multi-stability with various initial values resulting in an infinite number of coexisting attractors is also revealed. Finally, the proposed attractor is implemented using the Field Programmable Gate Array (FPGA) platform and building analog circuit based on Multisim. Among which, the former is potentially used to design the Pseudo-random signal generator in information encryption, while the latter is for verifying the existence of the proposed chaotic system.

Miura-ori based reconfigurable multilayer absorber for high-efficiency wide-angle absorption.

Radar stealth structures that can achieve high-efficiency wide-angle absorption are key components of future military equipment. However, it is difficult for both planar and three-dimensional (3D) absorbers to achieve efficient absorption in a large incidence angle range. The multilayer reconfigurable absorber component based on Miura origami provides a unique solution. First, the multilayer origami absorber is parameterized in the simulation software. Each origami structure is covered with resistive films that fit the panels. Geometric constraints are satisfied among the multilayer structures. They support reconfigurability in the range of continuous states (as opposed to discrete states), which is conducive to finding the folded state with a more efficient absorption rate within the frequency band. Secondly, the designed structure does not require a specialized mechanically supported multilayer origami absorber. In addition, the equivalent analogue circuit method is used to analyze the efficient absorption of multilayer origami under oblique incidence. Finally, our proposed absorber satisfies the requirements of multiple absorption metrics: broadband, high efficiency, wide incidence angle, and polarization insensitivity. As the validation, we simulated and fabricated a double-layer origami absorber. Our proposed origami absorber can maintain an absorption rate of more than 90% for both transverse electric (TE) and transverse magnetic (TM) polarizations in the operating frequency band (5-20 GHz) over a wide range of incidence angles (0°-70°). When the incidence angle qinc = 40°, the double-layer origami absorber (q1 = 90°, α1 = 60°, and a2 = 75°) can achieve at least 10 dB reflection reduction of -18 dB and -20 dB in TE and TM modes, respectively. The proposed origami absorber provides a reference for the design of other absorbers.

Impact of varying channel length on Analog/RF performances in a novel n-type silicon-based DG-JLT

Shrinking MOSFETs suffer performance hits due to short-channel effects and leakage. Junctionless transistors JLTs emerge as promising alternatives due to simpler fabrication and better gate control. This paper investigates the analog and RF performance characteristics of n-type Silicon-Based Double Gate Junctionless Transistors with varying channel lengths (15 nm, 20 nm, and 25 nm) This study evaluates analog device performance through critical parameters: drain current density (Id), transconductance (gm), output resistance (RO), intrinsic gain (gmRO), and transconductance generation factor (gm/Id). These parameters assess current handling, gain characteristics, and design efficiency, providing a comprehensive analysis for analog circuit applications. Results indicate that the device having 15 nm channel length exhibits a transconductance which is 25.38 % more than the 20 nm variant and drain current which is 44.7 % more than the latter, suggesting its superior performance to devices with longer channel lengths. In addition, the RF performance of the devices is evaluated using the small signal model of the device. This work further investigates the high-frequency response of the devices using key figures of merit (FoMs): gate capacitances (Cgs, Cgd, Cgg), cut-off frequency (fT), and maximum oscillation frequency (fMAX). These parameters quantify the influence of parasitic capacitances on switching speed and the maximum useable frequency for analog and RF applications. Analyzing Cgs, Cgd, and Cgg reveals the impact of gate control on high-frequency operation. The device having 15 nm channel length, exhibits an increase of 47.29 % in fT and 68.97 % increase in fMAX compared to device having 20 nm channel length. The findings underscore the significance of channel length optimization in enhancing the Analog and RF performance of n-type Silicon-based Double Gate Junctionless Transistors.

A Complex Analog Circuit Fault Diagnosis Method based on IMODA Improved Deep Belief Network

Aiming at the problems of time-consuming and low diagnosis accuracy during the unsupervised training process of traditional DBN, an analog circuit fault diagnosis method based on Improved Multi-Objective Dragonfly Optimized Deep Belief Network (IMODA-ADBN) is proposed. The method employs an improved MODA algorithm instead of the BP algorithm, which improves the classification accuracy of the network and ameliorates the problem of being prone to falling into local optima. The algorithm is tested on three multi-objective mathematical benchmark problems and compared with three well-known meta-heuristic optimization algorithms such as MODA, MOPSO and NSGA-II, and the results demonstrate the stability of the IMODA-ADBN network model. Finally, IMODA-ADBN is applied to the diagnostic experiments of a two-stage quad op-amp dual second-order low-pass filter, and the results show that the method improves the classification accuracy and diagnostic rate while guaranteeing the convergence speed, and is able to effectively realize the classification and localization of difficult faults.

An Efficient Double Deep Q Learning Network-Based Soft Faults Detection and Localization in Analog Circuits

To identify whether the circuit under test is fault-free or faulty, fault diagnosis is conducted in an analog circuit. However, in the case of fault detection (FD) techniques, the size of FD is the main challenge in testing, especially for complex analog circuits. Hence to reduce the size of FD, specific test nodes are chosen to perform fault diagnosis from the available accessible test nodes. Specific test nodes are selected based on the faults classification efficiency of fault diagnosis. Therefore, this paper proposes an approach for single and multiple soft fault diagnosis using minimum test nodes in analog electronic circuits. The proposed double deep Q-learning-based hybrid Simulated annealing–Tabu search (DDQN-Hybrid SATS) technique determines minimum test nodes with the utilization of distance metric for fault classification. The DDQN-Hybrid SATS technique is used to identify minimum nodes for testing. In this, the double deep Q learning network (DDQN) ensures better reliability and faster convergence in learning but suffers from catastrophic forgetting issues. To prevent such issues, the DDQN approach is optimized using a hybrid SATS algorithm. The hybrid optimization of simulated annealing (SA) and Tabu search (TS) coalesce the advantages of individual optimization procedures to provide the optimum solution in a fast and effective way. The results for a fourth-order low pass filter are presented (i.e., first CUT) and an eight-bit digital to analog converter (i.e., second CUT). Moreover, the simulation experiment reveals that the proposed DDQN-Hybrid SATS technique achieves greater overall fault classification accuracy of about 96.25% than other compared techniques with minimum computation time.

A Fault Diagnosis Method for Analog Circuits Based on Improved TQWT and Inception Model

A soft fault in an analog circuit is a symptom where the parameter range of a component exists symmetrically to the left and right of its nominal value and exceeds a specific range. The proposed method uses the Grey Wolf Optimization (GWO) optimized tunable Q-factor wavelet transform (TQWT) algorithm for feature refinement, the Inception model for feature extraction, and an SVM for fault diagnosis. First, the Q-factor is optimized to make it more compatible with the signal. Second, the signal is decomposed, and a single-branch reconstruction is performed using the TQWT to extract features adequately. Then, fault feature extraction is conducted using the Inception model to obtain multiscale features. Finally, a Support Vector Machine (SVM) is used to complete the entire fault diagnosis process. The proposed method is comprehensively evaluated using the Sallen–Key bandpass filter circuit and the four-op-amp biquad high-pass filter circuit widely used in electronic systems. The experimental results prove that the proposed method outperforms the existing methods in terms of diagnosis accuracy and reliability.

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

This paper provides a detailed exploration of CMOS operational amplifiers (Op-Amps) aimed at enhancing understanding of their development, design, and application. To achieve this, a comprehensive examination of the common characteristics, parameters, and bibliographic reviews of Op-Amps, distinguishing among various chosen operational amplifiers. A comprehensive bibliographic review of the operational amplifier's keywords between 2008 and 2018 has also been conducted. A bibliometric analysis of 4997 documents from the Web of Science (WOS) Collection is conducted using VOSviewer software. Furthermore, an analysis and comparison of these Op-Amps across functional aspects relevant to industrial and biomedical applications, emphasising the salient characteristics of each technique. After the survey, a novel Op-Amp design is proposed, incorporating a differential amplifier at the first stage, along with a compensating capacitor and a high gain stage. The biasing circuitry is replaced with an active load resistor (MOS transistor), simplifying layout design, and reducing the amplifier's area and power consumption compared to traditional two-stage designs. The power source for this design is 3.3 V. This designed operational amplifier achieved a gain of 62.9449 dB, a high CMRR of 92.8079 dB, and a unity gain bandwidth of 33 MHz, and the optimised layout area is 0.001476 μm2. The proposed circuit was designed and simulated utilising the Cadence Virtuoso 180 nm CMOS process. The simulation results show that the desired criteria have been met. Additionally, the challenges and future possibilities in analog circuits, laying the groundwork for research in both analogue and digital circuits to tackle complex real-world issues have been addressed.

The signal compensation method for the neutron flux in the measurement system using self-powered neutron detector.

Self-powered neutron detectors (SPNDs) have been utilized within in-core instrumentation to measure neutron flux for control and core flux mapping in nuclear reactors. To estimate neutron flux with SPNDs, a mathematical dynamic model correlating neutron flux and SPND material has been established. Estimation and signal compensation for neutron flux have primarily been developed using transfer-function-based methods or state-space-based methods. Particularly for the rhodium SPND, to compensate for its delayed response to incident neutron flux input, both groups of compensation methods have been widely applied. This Review details the signal compensation methods of neutron flux using transfer-function-based methods, such as those employing analog circuits, dynamic modeling of neutron flux, compensation of neutron flux, and direct inversion. In addition, signal compensation and estimation of neutron flux using state-space-based methods, such as the Kalman filter and H-infinity filter, are reviewed, along with basic calculations based on certain assumptions. Since there are differences in the characteristics of the two groups of methods for the same type of SPND, review comments are also included regarding the stability of compensation methods, based on results obtained from calculations using certain assumptions.

Influence of CoSi Oxidation and Passivation During Silicide Selective Etching on Junction Leakage: Applications to Schottky Diodes Devices

For new analogic microelectronic circuits development based on non-linear devices such as Schottky diodes formed in Si active regions, new Co-silicide integrations are required to reduce junction leakages. To gather targeted device requirements, precise Co silicide/Si interface optimization and a limited silicide formation at the active edges is needed. The selective etching during the “Salicide” process plays a real role in the oxidation and/or passivation of the silicide layer. Here, we propose a systematic study including a very large spectrum of experiments around the main parameters of CoSi selective etching. The main conclusions are (1) diode leakages are directly linked to SiO2 layer thickness formed during the SC1 dispense or by air exposure over the CoSi layer, (2) significant effect of dispense flow on SiO2 formation is measured through X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry characterizations; (3) optimized diode leakages together with contact resistances are then demonstrated for low SC1 delivery flow and long dispense time; and (4) major changes in final CoSi2 layer morphology and silicide/silicon interface are observed by transmission electron microscopy-energy-dispersive X-ray analyses for different selective etching processes, which are potentially explained by enrichment in Co atoms at CoSi/Si during SiO2 overlayer growth.

A Briefly Survey in Electronics System Design

In this paper, it will be tried to briefely talk about electronic system design. In these 20 years, electronic system such as other sciences has improved. From analog and digital circuits toward nano bio systems. It will be discussed the main methods of electronic system design not only in analog and digital systems but also about nano and bio electronics systems.

Novel GA‐OCEAN Framework for Automatically Designing the Charge‐Pump Circuit

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Detecting and Classifying Parametric Faults in Analog Circuits Using an Optimized Attention Neural Networks

Detecting and Classifying Parametric Faults in Analog Circuits Using an Optimized Attention Neural Networks

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

A Concise 4D Conservative Chaotic System with Wide Parameter Range, Offset Boosting Behavior and High Initial Sensitivity

In this paper, we present a concise four-dimensional (4D) conservative chaotic system with a wide parameter range. Since there are no terms higher than first order, the circuit does not contain multipliers, resulting in a simple circuit implementation. The nonlinear dynamic characteristics, such as phase diagrams, equilibrium points, divergence, Poincaré cross-sections, Lyapunov exponents, bifurcation diagrams, and Lyapunov dimension, are analyzed in detail, which illustrates the conservativity. Besides, the system exhibits different offset boosting behaviors. Through offset boosting, the system can propagate along a line, convert signal polarity, control variable amplitude, generate coexisting attractors, and even induce changes in its state. Specially, we realize the transition from a single-vortex attractor to a multivortex one by some changes in the initial values. Furthermore, the Pearson correlation coefficient is used to demonstrate the higher initial value sensitivity of the system. Finally, the system is implemented through Multisim simulation and analog circuit separately, and their consistency validates the system effectively.

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.