Analog Baseband Research Articles

Parallel Digital Predistortion Design on Mobile GPU and Embedded Multicore CPU for Mobile Transmitters

Digital predistortion (DPD) is a widely adopted baseband processing technique in current radio transmitters. While DPD can effectively suppress unwanted spurious spectrum emissions stemming from imperfections of analog RF and baseband electronics, it also introduces extra processing complexity and poses challenges on efficient and flexible implementations, especially for mobile cellular transmitters, considering their limited computing power compared to basestations. In this paper, we present high data rate implementations of broadband DPD on modern embedded processors, such as mobile GPU and multicore CPU, by taking advantage of emerging parallel computing techniques for exploiting their computing resources. We further verify the suppression effect of DPD experimentally on real radio hardware platforms. Performance evaluation results of our DPD design demonstrate the high efficacy of modern general purpose mobile processors on accelerating DPD processing for a mobile transmitter.

Reference Receiver Enhanced Digital Linearization of Wideband Direct-Conversion Receivers

This paper proposes two digital receiver (RX) linearization and in-phase/quadrature (I/Q) correction solutions, where an additional reference RX (ref-RX) chain is adopted in order to obtain a more linear observation, in particular, of the strong incoming signals. This is accomplished with reduced RF gain in the ref-RX in order to avoid nonlinear distortion therein. In digital domain, the signal observed by the ref-RX is exploited in linearizing the main RX. This allows combining the sensitivity of the main RX and the linearity of the lower gain ref-RX. The proposed digital processing solutions for implementing the linearization are feedforward interference cancelation and nonlinearity inversion, which are both adapted blindly, without a priori information of the received signals or RX nonlinearity characteristics. The linearization solutions enable flexible suppression of nonlinear distortion stemming from both the RF and analog baseband components of different orders. Especially, wideband multicarrier RXs, where significant demands are set for the RX linearity and I/Q matching, are targeted. Using comprehensive RF measurements and realistic base-station scale components, an RX blocker tolerance improvement of 23 dB and a weak carrier signal-to-noise-and-distortion ratio gain of 19 dB are demonstrated with combined linearization and I/Q correction.

A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar

A fully-integrated 77 GHz frequency doubling two-path phased-array frequency-modulated continuous-wave (FMCW) transceiver for automotive radar applications is proposed. By utilizing the frequency doubling scheme, the chirp bandwidth is improved, and the complexity of the frequency synthesizer and the insertion loss of the local-oscillating (LO) distribution network are both reduced. Top-injected coupled resonator based wide locking range technique is proposed in the frequency doublers to minimize the required injection power to cover the chirp bandwidth plus enough PVT variation margin, and therefore reduce the power consumption of the LO distribution network. Current-reused coupled resonator technique is utilized to implement the LO phase shifting in each receiving path. The digitally controlled artificial dielectric-based transmission lines are inserted in the low noise amplifiers to provide the operation frequency calibration capability. The receiving two-path signals are converted into intermediate frequency by low flicker noise current-mode passive mixers and then combined in the trans-impedance amplifier, followed by the reconfigurable analog baseband processing. Fabricated in 65 nm CMOS, the FMCW transceiver has achieved 1.93 GHz maximum chirp bandwidth, 12.9 ~ 13.2 dBm maximum transmitting power, and 47.8 ~ 100.7 dB programmable receiving conversion gain. The transceiver consumes 343 mW power and 4.64 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area including all of the pads.

Double Dielectric Slab-Loaded Air-Filled SIW Phase Shifters for High-Performance Millimeter-Wave Integration

Phase shifters based on double dielectric slab-loaded air-filled substrate-integrated waveguide (SIW) are proposed for high-performance applications at millimeter-wave frequencies. The three-layered air-filled SIW, made of a low-cost multilayer printed circuit board process, allows for substantial loss reduction and power handling capability enhancement compared with the conventional dielectric-filled counterpart. It is of particular interest for millimeter-wave applications that generally require low-loss transmission and high-density power handling. Its top and bottom layers may make use of a low-cost standard substrate, such as FR-4, on which baseband analog or digital circuits can be implemented so to obtain very compact, low cost, and self-packaged millimeter-wave integrated systems compared with the systems based on rectangular waveguide while achieving higher performance than the systems based on the conventional SIW. In this paper, it is demonstrated that transmission loss can be further improved at millimeter-wave frequencies with an additional polishing of the top and bottom conductor surfaces. Over Ka-band, an improvement of average 1.56 dB/m is experimentally demonstrated. Using the air-filled SIW fabrication process, dielectric slabs can be implemented along conductive via rows without any additional process. Based on the propagation properties of the obtained double dielectric slab-loaded air-filled SIW, phase shifters are proposed. To obtain a broadband response, an equal-length compensated phase shifter made of two air-filled SIW structures, offering a reverse varying propagation constant difference against frequency, is proposed and demonstrated at Ka-band. Finally, a single dielectric slab phase shifter is investigated for comparison and its bandwidth limitation is highlighted.

A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS

A discrete-time (DT) analog baseband for software-defined-radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable $\mathrm {g}_{\mathrm {m}}$ is converted to current, which is integrated on a 5th-order DT infinite-impulse response (IIR) low-pass filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates selected samples to implement active finite-impulse-response (FIR) filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10 bit successive approximation (SAR) ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/ $\surd $ Hz input-referred noise and 52 dB gain range while consuming a maximum power of 15 mW.

Design of a fully integrated receiver analog baseband chain for 2.4-GHz ZigBee applications

A receiver analog baseband (ABB) chain for an integrated ZigBee (IEEE 802.15.4) transceiver is presented in this paper. The ABB is composed by a 3rd-order complex band-pass filter (BPF), a variable gain amplifier (VGA) and an analog-to-digital converter (ADC). The circuit topology of each building block has been designed complying with the IEEE 802.15.4 standard as well as featuring low power consumption and small chip size. In this work, a mixed-signal frequency auto-tuning scheme is proposed for complex BPF to accommodate the performance deterioration due to the process, voltage and temperature (PVT) variations. A novel method combined opamp- and capacitor-sharing is presented for ADC to obtain low power consumption and elimination of memory effect. The proposed ABB demonstrates 70dB dynamic range by 2dB/step, 12dBm IIP3 and 35.2nV/√Hz input referred noise. The measured SNDR and SFDR are 41.9dB and 58.7dB, respectively. Implemented in a standard 0.18-μm CMOS technology, the entire receiver ABB chain occupies an area as small as 1.5mm2 and the total power consumption is only 16mW at max gain setting from a 1.8V supply.

Mm-wave integrated wireless transceiver: enabling technology for high bandwidth short-range networking in cyber physical systems

Emerging application scenarios for Cyber Physical Systems often require the networking of sensing and actuation nodes at high data rate and through wireless links. Lot of surveillance and control systems adopt as input sensors distributed video cameras operating at different spectral ranges and covering different fields of view. Arrays of radio/light detection and ranging (Radar/Lidar) sensors are often used to detect the presence of targets, of their speeds, distance and direction. The relevant bandwidth requirement amounts to some Gbps. The wireless connection is essential for easy and flexible deployment of the sensing/actuation nodes. A key technology to keep low the size and weight of the nodes is the fully integration at mm-waves of wireless transceivers sustaining Gbps data rate. To this aim, this paper presents the design of 60 GHz transceiver key blocks (Low Noise Amplifier, Power Amplifier, Antenna) to ensure connection distances up to 10 m and data rate of several Gbps. Around 60 GHz there are freely-available (unlicensed) worldwide several GHz of bandwidth. By using a CMOS Silicon-on-Insulator technology RF, analog and digital baseband circuitry can be integrated single-chip minimizing noise coupling. At mm-wave the wavelength is few mm and hence even the antenna is integrated on chip reducing cost and size vs. off-chip antenna solutions. The proposed transceiver enables at physical layer the implementation in compact nodes of links with data rates of several Gbps and up to 10 m distance; this is suited for home/office scenarios, or on-board vehicles (cars, trains, ships, airplanes) or body area networks for healthcare and wellness.

A Low Voltage Tunable Filter for Analog Baseband of Software Defined Radios

A Low Voltage Tunable Filter for Analog Baseband of Software Defined Radios

Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications

In this paper, a receiver front-end tailored to Bluetooth Low Energy applications is presented. In the proposed solution, the LNA, mixers, VCO, quadrature scheme and the first stage of the analog base-band share the same bias current under a 0.8 V voltage supply leading to a sub-mW power consumption. A channel selection filter, implemented through a current re-use gm-C topology, completes the design. The presented prototype, realized in 130 nm CMOS technology, occupies an active area of 0.25 mm $^{2}$ while consuming only 0.6 mW. With a NF of 15.8 dB, an IIP3 of $-$ 17 dBm at the maximum gain and an image rejection above 30 dB the receiver front-end meets BLE noise figure, image rejection, phase noise and linearity requirements.

An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation

In-band full-duplex (FD) wireless, i.e., simultaneous transmission and reception at the same frequency, introduces strong self-interference (SI) that masks the signal to be received. This paper proposes a receiver in which a copy of the transmit signal is fed through a switched-resistor vector modulator (VM) that provides simultaneous downmixing, phase shift, and amplitude scaling and subtracts it in the analog baseband for up to 27 dB SI-cancellation. Cancelling before active baseband amplification avoids self-blocking, and highly linear mixers keep SI-induced distortion low, for a receiver SI-to-noise-and-distortion-ratio (SINDR) of up to 71.5 dB in 16.25 MHz BW. When combined with a two-port antenna with only 20 dB isolation, the low RX distortion theoretically allows sufficient digital cancellation for over 90 dB link budget, sufficient for short-range, low-power FD links.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760–960 MHz and 2.4–2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers

This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the top-level chip floorplan. It is shown that the proposed structure does not introduce extra power consumption compared to the conventional approach, while obtaining a higher SNR. A four-antenna-path version of the proposed topology is implemented in 40 nm low-power CMOS as a prototype together with a variable gain block forming a complete analog baseband section for a phased-array receiver. The functionality includes beamforming with a resolution better than 6.8 degrees, fourth-order lowpass filtering with a 1 GHz cutoff frequency, variable gain between 10.6 and 30 dB and automatic DC offset compensation. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for 16-QAM modulation according to IEEE 802.11ad. The circuit consumes between 30 and 42 mW.

A 85-mW Multistandard Multiband CMOS Mobile TV Tuner for DVB-H/T, T-DMB, and ISDB-T Applications with FM Reception

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a 0.18-mm CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T- DMB, and ISDB-T with a digital demodulator.

A broadband CMOS RF receiver for digital broadcasting systems

Nowadays digital radio systems are replacing analog radio systems. In this paper, a CMOS RF receiver with frequency synthesizer and analog baseband is introduced, which was fabricated with a 0.18-µm CMOS process for DRM/DAB wideband applications. In the system, a fully differential low noise amplifier with a noise cancelling technology is adopted It has achieved a gain of 11.69 dB. A harmonic rejection mixer was implemented to realize the rejections of 3rd- and 5th-order harmonics. As the local oscillator, a wide-band frequency synthesizer provides a phase noise of ?125 dBc/Hz at 1-MHz offset. The designed RF receiver has achieved a conversion gain of 90 dB. The IIP3 of the receiver is in the range of ?25 to ?12 dBm, and the noise figure of 5.44---14.72 dB. The core circuits draw a current of 78.35 mA from a 1.8-V power supply and the chip occupies 6.46-mm2 die area.

A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

A 4.8-mm $^{2}~0.1$ –6.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A simple approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the power-scalable and feedforward compensation techniques, the power of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a low-power subpath to cooperatively cover different standards over 0.1–6.0 GHz with more flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with efficiency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <−50-dBc image rejection ratio and <−40-dBc local oscillating signal leakage after the calibration. System verifications have demonstrated −31/−51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the main path and 1.7% error vector magnitude (EVM) at 1.5-dBm output for 1.8-GHz WCDMA in the subpath. Both paths enable SAW-less FDD operations with −153 or −156 dBc/Hz carrier-to-noise ratio at 200-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and 0.8%, respectively, and exhibiting the intraband CA capability.

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-&lt;roman&gt;nm&lt;/roman&gt; CMOS

A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational amplifier (Opamp) for the proposed MABB can reduce the GBW, as long as it meets the GBW requirement for different BW, gain, and order. A flexible power-efficient high-GBW Opamp with an adaptive common-mode bias circuit is also proposed for the eighth-order active-RC MABB. The proposed MABB covers a cutoff frequency range from 200 kHz to 20 MHz, whereas the gain could be tuned between 0 and 72 dB. The proposed highly reconfigurable MABB is suitable for multistandard integrated wireless receivers.

Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process. The circuit comprises a 3rd-order active-RC complex filter (CF) and a programmable gain amplifier (PGA). An automatic tuning circuit is also designed to tune the CF's pass band. Instead of the class-A fully differential operational amplifier (FDOPA) adopted in the conventional CF and PGA design, a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption. In the PGA circuit, a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly. A reformative switching network is proposed, which can eliminate the switch resistor's influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10–50 dB with a 1-dB step size, and the gain accuracy is less than ±0.3 dB. The OIP3 is 23.3 dBm at the gain of 10 dB. Simulation results show that the settling time is reduced from 100 to 1 ms. The image band rejection is about 40 dB. It only draws 4.5 mA current from a 1.8 V supply voltage.

System design considerations of universal UHF RFID reader transceiver ICS

This paper describes the architecture, system analysis and implementation of world-wide regulation compliant UHF RFID reader transceiver for ISO 18000-6 multi-class tags in the ISM band 860 MHz-960 MHz. The presented considerations are based on a system analysis providing evaluation of the transceiver?s building blocks parameters in accordance with the required characteristics of a complete RFID reader system, read range, data transmission rate, reading speed and power consumption. The Phase Noise, Noise Figure, Sensitivity, P1dB, Dynamic Range are estimated for the design of a custom ?system-in-package? transceiver, implemented in LTCC-module. Based on the direct-conversion architecture, the reader transceiver integrates RF-blocks, frequency synthesizer, modulation and demodulation functions, low frequency analog baseband. The receiver sensitivity is down to -85 dBm, the transmitter produces output power of +17 dBm.

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15MHz LP bandwidth, 2–8MHz CBP bandwidth and 0–36dB gain range with 1dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65nm CMOS. It achieves 15.2dBm/27.1dBm IB/OB-IIP3, −2dBm IP1dB and 71dBm IIP2 while consuming 3.6–9.1mW from a 1.2V power supply and 0.75mm2 chip area.