Calibration Of Analog-to-digital Converters Research Articles

Intan Technologies integrated circuits can produce analog-to-digital conversion artifacts that affect neural signal acquisition

Objective. Intan Technologies’ integrated circuits (ICs) are valuable tools for neurophysiological data acquisition, providing signal amplification, filtering, and digitization from many channels (up to 64 channels/chip) at high sampling rates (up to 30 kSPS) within a compact package (⩽9× 7 mm). However, we found that the analog-to-digital converters (ADCs) in the Intan RHD2000 series ICs can produce artifacts in recorded signals. Here, we examine the effects of these ADC artifacts on neural signal quality and describe a method to detect them in recorded data. Approach. We identified two types of ADC artifacts produced by Intan ICs: 1) jumps, resulting from missing output codes, and 2) flatlines, resulting from overrepresented output codes. We identified ADC artifacts in neural recordings acquired with Intan RHD2000 ICs and tested the repeated performance of 17 ICs in vitro. With the on-chip digital-signal-processing disabled, we detected the ADC artifacts in each test recording by examining the distribution of unfiltered ADC output codes. Main Results. We found larger ADC artifacts in recordings using the Intan RHX data acquisition software versions 3.0–3.2, which did not run the necessary ADC calibration command when the inputs to the Intan recording controller were rescanned. This has been corrected in the Intan RHX software version 3.3. We found that the ADC calibration routine significantly reduced, but did not fully eliminate, the occurrence and size of ADC artifacts as compared with recordings acquired when the calibration routine was not run (p < 0.0001). When the ADC calibration routine was run, we found that the artifacts produced by each ADC were consistent over time, enabling us to sort ICs by performance. Significance. Our findings call attention to the importance of evaluating signal quality when acquiring electrophysiological data using Intan Technologies ICs and offer a method for detecting ADC artifacts in recorded data.

A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost

AbstractThis paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network. Due to the non‐linear function fitting capability of the neural network, the linearity of the ADC is improved effectively. However, the hardware complexity of the neural network limits its application and promotion in ADC calibration. Hence, this paper also presents the optimization schemes, including the neuron‐based sharing neural network and the partially binarized with fixed neural network, in terms of calibration architecture and algorithm. A 60 MS/s 14‐bit pipelined‐SAR ADC prototyped in 28‐nm technology is utilized to verify the feasibility of the proposed calibration method. The measurement results show that the proposed calibration greatly enhances the Spurious Free Dynamic Range (SFDR) and Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) from low frequency to Nyquist frequency. Meanwhile, the original calibrator and improved calibrator are synthesized in Synopsys Design Compiler to compare their hardware complexity. Compared with the unoptimized version, the optimized schemes can decrease the logic area and the network weights up to 76% and 52%, with negligible loss in calibration performance.

Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS.

This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.

A short review of some analog-to-digital converters resolution enhancement methods

The resolution of the analog-to-digital converter (ADC), i.e. the minimum voltage that ADC can recognize, is an important indicator of ADC performance. In order to improve the accuracy of ADCs, some approaches are proposed to enhance the resolution of ADC. This paper presents a review of ADC resolution enhancement schemes, which includes the introduction of primary features, the explanation of basic principles, as well as their merits, demerits, and trade-offs. It describes a variety of resolution enhancement schemes from different aspects such as signal processing, ADC calibration, and novel acquisition architectures, and analyzes their applicable scenes. Finally, some challenges and issues are briefly summarized, as well as some comments on future work in this field. By reviewing the current literature, we can make recommendations on the design of acquisition system resolution according to the actual requirements.

Nonlinear error analysis and calibration model for cyclic ADCs in large array CMOS image sensors

A mathematical model is established to study the impact of nonlinear errors on the performance of cyclic analog-to-digital converters (ADCs) and imaging quality of CMOS image sensors (CIS). And a radix-based foreground digital calibration method for cyclic ADCs in large array CIS is proposed and modeled. The nonlinear errors caused by capacitor mismatch and finite operational amplifier (OPAMP) gain are mainly studied. Simulation results show that the proposed calibration method based on the statistical characteristics of large array CIS can effectively reduce the influence of nonlinear errors, greatly improve ADC linearity under large capacitor mismatch and finite OPAMP gain. In a CIS with 1500 columns of parallel ADCs, when the capacitor mismatch and OPAMP gain are 1% and 40 dB respectively, the effective number of bits (ENOB) of the calibrated ADC can be increased from about 6bit to 13bit. These results provide a new guideline for the calibration of cyclic ADCs in large array CMOS image sensors.

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration

This article presents a compact power management solution for a pipeline analog-to-digital converter (ADC), employing only a switching-mode power converter. By directly powering the ADC using a boost DC-DC converter, the power delivery network (PDN) exhibits an overall-high power efficiency. The proposed foreground ADC calibration calibrates the ripple error induced from the power converter, which obviates the need for well-regulated supply and reference voltage offered by low-efficiency linear low-dropout regulators (LDOs). A chip integrates the boost DC-DC converter and the pipelined ADC with an external power inductor. The prototype, implemented in 65-nm CMOS, occupies 2.34-mm2 of total active area (9.4% - ADC, 2.6% - power controller and switches, and 88% - output capacitance). In the measurement, the boost converter, switching at 31.25MHz, converts a 0.5V input to 1.2V and delivers 22.8mW of power to the pipeline ADC. The boost DC-DC converter supplies all voltage domains, including analog/digital power supply and reference. The resulting overall system power efficiency is 78.6%. Sampled at 500MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 34.7/39.9dB without/with the ripple calibration for an input frequency of 177MHz, respectively.

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

Pipeline analog-to-digital converters (ADCs), which dominated high-speed and high-resolution applications, suffered from weak improvement in power efficiency. To address such a problem, this brief presents a 14-bit split-pipeline opamp-sharing ADC, with background calibration that optimizes duty-cycle ratio and amplifier power consumption in the shared opamp. Based on the interstage gain (that includes settling) error estimated by the split ADC calibration engine, the clock duty-cycle ratio and the bias current are adjusted to achieve better dynamic settling and resolution trade-offs. Operating at 100 MS/s with a 9-MHz input signal, the ADC achieves 46.5 dB of signal-to-noise-and-distortion ratio (SNDR) and 59.6 dB of spurious-free dynamic range (SFDR) before calibration, and after calibration, it improves to 71.7 dB of SNDR and 84.4 dB of SFDR, respectively. The ADC maintains an SNDR over 68.5 dB within the full Nyquist bandwidth consuming 32 mW of power, which yields a Walden figure-of-merit (FoM) of 147.2 fJ/conversion-step and a Schreier FoM of 160.4 dB.

Calibration and Dynamic Matching in Data Converters: Part 2: Time-Interleaved Analog-to-Digital Converters and Background-Calibration Challenges

Part 1 of this article series, and Dynamic Matching in Data Converters: Part 1: Linearity Calibration and Dynamic-Matching Techniques, considered the calibration of digital-to-analog converters (DACs), dynamic element matching, and the calibration of pipelined analog-to-digital converters (ADCs). In this second part, the calibration of time-interleaved ADCs is covered first. Then challenges created by background calibration in the architectures described in both parts are covered. Finally, conclusions are drawn based on the examples in both parts.

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.

Volterra kernels measurement and the application in post calibration of ADCs

As the proper choice for the digital post-calibration of the Analog to Digital Converters (ADCs), Volterra series has developed on a firm mathematical and logical foundation for decades. The most important issue in the Volterra series method is how to measure the Volterra kernels. This paper describes how frequency domain Volterra kernels effectively separated by compounding the Vandermonde matrix.

An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

An offset double conversion technique to calibrate pipelined analog-to-digital converters (ADCs) is presented, in which self-equalization is performed using one ADC, resulting in fast convergence for high-resolution applications. The approach also promises significant improvement of signal-to-noise-plus-distortion ratio (SNDR), simultaneous multistage calibration, and minimal analog circuit modification. The design tradeoffs involved in this technique, especially the conversion rate reduction, are discussed in detail. Behavioral simulation results are presented to demonstrate the effectiveness of the technique, in which the learning of 39 error parameters is simultaneously accomplished with SNDR and spurious-free dynamic range improvements from 43 and 52 dB to 90 and 108 dB, respectively, for a 15-bit pipelined ADC.

System embedded ADC calibration for OFDM receivers

This paper describes a background calibration technique for analog-to-digital converters (ADCs) that exploits communication protocol redundancy to measure and correct for analog circuit imperfections. In particular, we consider the implementation of a 6-bit, 500-MS/s ADC in the receiver of an ultra wideband system using orthogonal frequency division multiplexing (OFDM). The calibration is intended for a time-interleaved array of successive approximation register ADCs and cancels converter nonlinearity due to inter-channel offset mismatches. The individual channel offsets are estimated through statistical correlation, based on known pseudorandom modulation sequences used in OFDM pilot tones. Our simulation results show that the proposed calibration is capable of improving the signal-to-noise and distortion ratio from 20 to 37 dB with a tracking time constant of 85 ms, assuming an additive white Gaussian noise channel with 20-dB signal-to-noise ratio

Performance improvement of all-digital wide-bandwidth receivers by linearization of ADCs and DACs

This paper will discuss recent advances in dynamic compensation of both analog to digital converters (ADCs) and digital to analog converters (DACs) for application in all-digital wide-bandwidth receivers. An overview of previous calibration and compensation procedures will be given. Recent ADC calibration procedures will be presented which speed the calibration process by several orders of magnitude. These procedures have been developed to allow for recalibration of an ADC outside of a laboratory environment. Calibration and compensation of DACs is also discussed. Highly linear DACs are desirable, since they may be used as calibration sources for ADCs, and are often fundamental building-blocks of high-resolution ADCs.

Comments on "Comments on "Interstage gain-proration technique for digital-domain multistep ADC calibration

This paper emphasizes that a gain-proration technique is required to correct the interstage gain error that occurs when multiple stages of a multistep analog-to-digital converter (ADC) are calibrated. It is shown that the interstage gain error critically affects ADC linearities, even if there is no other error including digital truncation errors except the interstage gain error. It is contrary to the comments in the commented paper [see ibid., vol. 46, p. 1114-7, 1999].

A calibration scheme for imperfect quantizers

This paper considers the calibration of imperfect quantizers, or analog-to-digital converters (ADCs). We present a method working purely in the digital domain, suitable e.g., for calibration of ADCs from output data only. The proposed method is based on a linear-filter reconstruction of an analog calibration signal. The reconstructed version of the calibration signal is employed in designing an updated quantization table, with the aim of improving the overall performance. Experiments demonstrate gains in terms of spurious-free dynamic range and signal-to-noise and distortion ratio (SNDR).