Analog-to-digital Research Articles

A 0.012‐mm2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

SummaryThis paper proposes a true random number generator (TRNG) based on a successive approximation register (SAR) analog‐to‐digital converter (ADC). A top‐plate sampling SAR ADC structure and a new MSB‐isolation switch scheme (MISS) are combined to achieve low‐power operation and small area occupancy at the same time. When the SAR ADC has completed its conversion, a secondary firing of the comparator measures the remaining signal. This 1‐bit quantized residue serves as the true random sequence, thus eliminating the need for extra circuitry in the TRNG. A 65‐nm prototype of the proposed TRNG was found to occupy an area of 0.012 mm2 and successfully passed all the National Institute of Standards and Technology (NIST) tests without post‐processing. It achieved a figure‐of‐merit of 0.244 pJ/bit for a 1 Mb/s random sequence with a 0.8‐V power supply. Its resilience to power noise injection attacks was also verified.

Sleep disturbances, cognitive decline, and AD biomarkers alterations in early Parkinson's disease.

We aimed to investigate whether each type of sleep disturbances (i.e., pRBD, EDS, and insomnia) is specifically associated with faster decline in global cognition and different cognitive domains among de novo PD patients. We also assessed the influence of sleep disturbances on core AD CSF biomarkers alterations and conversion to dementia. Prospectively longitudinal data were obtained from the PPMI cohort. Sleep disturbances and cognition ability were assessed by questionnaires at baseline and follow-up visits. Generalized linear mixed models were utilized to assess the effect of sleep disturbances on cognitive decline and core AD CSF biomarkers change. The associations between sleep disturbances and conversion to dementia were analyzed using Cox regression analysis. Baseline pRBD was associated with faster decline in global cognition and all cognitive domains, including verbal episodic memory, visuospatial ability, executive function, language, and processing speed. EDS was associated with faster decline in three cognitive domains, including verbal episodic memory, executive function/working memory, and processing speed. Insomnia was associated with faster decline in global cognition and verbal episodic memory. Meanwhile, pRBD and EDS were associated with longitudinal decrease of CSF Aβ42. Baseline pRBD increased the risk of conversion to dementia. The risk of dementia in PD patients with multiple sleep disturbances also increased compared with those without sleep disturbance. Sleep disturbances (i.e., pRBD, EDS, and insomnia) were associated with cognitive decline in early PD. EDS and pRBD were associated with decrease of CSF Aβ42. Moreover, pRBD was associated with conversion to dementia.

A Two-Year Observational Study to Evaluate Conversion Rates from High- and Low-Risk Patients with Amnestic Mild Cognitive Impairment to Probable Alzheimer's Disease in a Real-World Setting.

Predicting conversion to probable Alzheimer&s disease (AD) from amnestic mild cognitive impairment (aMCI) is difficult but important. A nomogram was developed previously for determining the risk of 3-year probable AD conversion in aMCI. To compare the probable AD conversion rates with cognitive and neurodegenerative changes for 2 years from high- and low risk aMCI groups classified using the nomogram. This prospective, multicenter, observational study was conducted in Korea. A total of patients were classified as high- or low-risk aMCI according to the nomogram and followed-up for 2 years to compare the annual conversion rate to probable AD and brain structure changes between the two groups. In total, 176 (high-risk, 85; low-risk, 91) and 160 (high-risk, 77; low-risk, 83) patients completed the 1-year and 2-year follow-up, respectively. The probable AD conversion rate was significantly higher in the high-risk (Year 1, 28.9%; Year 2, 46.1%) versus low-risk group (Year 1, 0.0%; Year 2, 4.9%, both p < 0.0001). Mean changes from baseline in Seoul Neuropsychological Screening Battery-Dementia Version, Clinical Dementia Rating-Sum of Box, and Korean version of the Instrumental Activities of Daily Living scores and cortical atrophy index at Years 1 and 2 were significantly greater in the high-risk group (p < 0.0001). The high-risk aMCI group, as determined by the nomogram, had a higher conversion rate to probable AD and faster cognitive decline and neurodegeneration change than the low-risk group. These real-world results have clinical implications that help clinicians in accurately predicting patient outcomes and facilitating early decision-making.Trial Registration: ClinicalTrials.gov (NCT03448445).

A neural network‐based error correction in the first‐stage residue of pipelined analog to digital converters

SummaryAn analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

Microcontroller-Optimized Measurement Electronics for Coherent Control Applications of NV Centers.

Long coherence times at room temperature make the NV center a promising candidate for quantum sensors and quantum computers. The necessary coherent control of the electron spin triplet in the ground state requires microwave π pulses in the nanosecond range, obtained from the Rabi oscillation of the mS spin states of the magnetic resonances of the NV centers. Laboratory equipment has a high temporal resolution for these measurements but is expensive and, therefore, uninteresting for fields such as education. In this work, we present measurement electronics for NV centers that are optimized for microcontrollers. It is shown that the Rabi frequency is linear to the output of the digital-to-analog converter (DAC) and is used to adapt the time length π of the electron spin flip, to the limited pulse width resolution of the microcontroller. This was achieved by breaking down the most relevant functions of conventional laboratory devices and replacing them with commercially available integrated components. The result is a cost-effective handheld setup for coherent control applications of NV centers.

Oxide semiconductor based deep‐subthreshold operated read‐out electronics for all‐printed smart sensor patches

AbstractThe ability to fabricate an entire smart sensor patch with read‐out electronics using commercial printing techniques may have a wide range of potential applications. Although solution‐processed oxide thin film transistors (TFTs) are capable of providing high mobility electron transport, resulting in large ON‐state current and power output, there is hardly any literature report that uses the printed oxide TFTs at the sensor interfaces. Here, printed amorphous indium‐gallium‐zinc oxide (a‐IGZO)‐based deep‐subthreshold operated TFTs that comprise signal amplifiers and analog‐to‐digital converters (ADCs) that can successfully digitalize the analog sensor signals up to a frequency range of 1 kHz are reported. In addition, exploiting the high current oxide TFTs, a current drive circuit placed after the ADC unit has been found useful in producing easy‐to‐detect visual recognition of the sensor signal at a predefined threshold crossover. Notably, the entire smart sensor patch is demonstrated to operate at a low supply voltage of ≤2 V, thereby ensuring that it can be an on‐chip energy source compatible and standalone detection unit.

A phase modulation method of sine signal for dual-active-valve piezoelectric pump

A phase modulation method with wide range and high resolution for the sine signal is essential for dual-active-valve piezoelectric pump (DAVPP) control. In DAVPP, by phase modulation, the flow direction can be changed and the output flow rate and pressure can be precisely adjusted. In this article, the authors developed a phase modulation method for the sine signal. This method is characterized by both the combination of hardware and software, and the combination of digital circuits and analog circuits. In hardware, a sinxcosϕ constructing circuit and a cosxsinϕ constructing circuit are specially structured, which enables phase modulation to be achieved. In software, the output phase is determined by the digital controlling quantities sent by the main control chip and stored in the form of a table. Analytical formulas for the cosine constructing table tab_cos and the sine constructing table tab_sin are analyzed and structured. Experimental results show that the output phase can be regulated linearly and continuously, within a range of 0°–360°. Its resolution can be improved according to the requirements. Although the modulation process and circuit are simple, it can effectively solve the problem of sine signal phase modulation for DAVPP control.

Fast switching hydrogen gas leakage identification using FPGA

Hydrogen will play a key part in the decarbonization of the global energy supply as the wealth of hydrogen continues to rise. However, applying hydrogen knowledge necessitates the installation of strong safety protocols, including the use of reliable hydrogen gas-detecting devices. Gas detection and monitoring at a large scale in industries need programmable electronic systems that can provide fast response and switching. The objective of the research work is to analyze the hydrogen gas detection system using a field programmable gate array (FPGA). The system is integrated with the gas sensor module, temperature control module, buzzer for alarm, liquid crystal display (LCD) and light-emitting diode (LED) for information display, and global system for mobile communication (GSM) for wireless message communication to the mobile. The temperatures module works on the sampling of the heater resistance using a voltage divider and inbuilt analog-to-digital converter (ADC), which depend on the output voltage of the digital-to-analog converter (DAC). The comparator module compares the gas concentration with the pre-decided threshold limit and acknowledges the buzzer accordingly. The system behavior for monitoring and gas concentration detection is simulated in Xilinx Vivado design suite 2020.1. The functionality of the chip is also verified in the Modelsim 10.0 waveform simulator. for the testbench tata sand samples used. LCD (16x2) displays the messages whether hydrogen gas is detected or not and the same message is delivered on mobile. The novelty of the work is that the system is applicable for faster switching in industrial applications and the designed system supported 550 MHz frequency in our simulation and synthesis.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators’ performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier’s differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator’s speed by more than 10%.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step.

Alternating Optimization Algorithms for Hybrid beamforming in mm wave MIMO systems

Millimeter wave (mmWave) interchanges has been viewed as a critical empowering innovation for 5G organizations, as it offers significant degrees more noteworthy range than current cell groups. As opposed to traditional various info numerous output (MIMO) frameworks, precoding in mmWave MIMO unable to performed completely at baseband utilizing computerized precoders, as just a predetermined no. of sign blenders and Analog to-digital converters (ADCs) can be upheld thinking about their expense and power utilization. Hybrid precoding transceiver design, joining a digital precoder and analog precoder, has as of late gotten impressive consideration. Nonetheless, the ideal plan of such half breed precoders has not been completely perceived. In this paper, treating the hybrid precoder plan as a lattice factorization issue, alternating minimization (AltMin) calculations will be proposed for two different half and half precoding structures, i.e., the completely associated what's more, somewhat associated structures. Specifically, for the fully connected structure, an AltMin calculation in view of complex advancement is proposed to move toward the exhibition of the completely computerized precoder, which, notwithstanding, has a high intricacy. Subsequently, a low-intricacy AltMin calculation is then proposed, by implementing a symmetrical limitation on the computerized precoder. Besides, for the to some degree associated structure, an AltMin calculation. Be that as it may, the ideal plan of is additionally evolved with the assistance of semidefinite unwinding. For commonsense execution, the proposed AltMin algorithms are additionally stretched out to the broadband setting with symmetrical recurrence division multiplexing (OFDM) adjustment. Recreation results will show critical execution gains of the proposed AltMin calculations over existing half breed precoding calculations. In addition, in light of the proposed calculations, recreation correlations between the two mixture precoding designs will give significant plan experiences.

Energy‐efficient switching method using input‐swapping for high‐resolution successive approximation register analog‐to‐digital converters

AbstractThis paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits.

A configurable ultra-low noise current source for transition-edge sensor characterization

Transition-edge sensors (TESs) are sensitive devices for detecting photons from millimeter radiation to γ rays. Their photon counting efficiency and collecting area benefit from large-array multiplexing scheme, and therefore the development of multiplexing readout system has been an important topic in this field. Among the many multiplex techniques, time-division multiplexing (TDM) superconducting quantum interference device (SQUID) has been used most widely for TES readout. In this work, we design a Configurable Ultra-Low Noise Current Source (CLCS) for TES characterization and as a part of a whole TDM-TES bias control system. The CLCS is based on the feedback structure of ultra-low noise instrumentation amplifiers and low-noise, high-resolution (20 bits) digital-to-analog converter (DAC). CLCS has an ultra-high resolution of 10 nA in the 0 to 5 mA current output range, and can perform current-voltage (IV) sweep and bias-step tests to measure key TES parameters on board. The feedback structure of the CLCS also avoids the issue of impedance mismatch.

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors.

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution.

In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than -10 dB.

Design of a Negative Temperature Coefficient Temperature Measurement System Based on a Resistance Ratio Model.

In this paper, a temperature measurement system with NTC (Negative Temperature Coefficient) thermistors was designed. An MCU (Micro Control Unit) primarily operates by converting the voltage value collected by an ADC (Analog-to-Digital Converter) into the resistance value. The temperature value is then calculated, and a DAC (Digital-to-Analog Converter) outputs a current of 4 to 20 mA that is linearly related to the temperature value. The nonlinear characteristics of NTC thermistors pose a challenging problem. The nonlinear characteristics of NTC thermistors were to a great extent solved by using a resistance ratio model. The high precision of the NTC thermistor is obtained by fitting it with the Hoge equation. The results of actual measurements suggest that each module works properly, and the temperature measurement accuracy of 0.067 °C in the range from -40 °C to 120 °C has been achieved. The uncertainty of the output current is analyzed and calculated with the uncertainty of 0.0014 mA. This type of system has broad potential applications in industry fields such as the petrochemical industry.

Design and Analysis of Micro Signal Detection Circuit for Magnetic Field Detection Utilizing Coil Sensors

Eddy current inspection has been extensively employed in non-destructive testing of various conductive materials. The coil probe, as a mainstream sensor in the eddy current detection system, inevitably encounters interference from external signals while transmitting its own signal. Therefore, developing techniques to extract valuable signals from noisy ones is crucial for ensuring accurate detection. Carbon fiber composites not only possess significantly lower electrical conductivity compared to conventional metallic materials but also exhibit notable anisotropy. To address this issue, we designed an ‘8’ coil probe set where the excitation coil does not electromagnetically interfere with the detection coil. However, practical applications that require portability and miniaturization pose challenges when utilizing this coil probe set to identify carbon content or defects due to the typically weak output signal. To address this issue, this paper proposes a design that combines the ‘8’ structure of the planar coil probe with the principle of phase-locked amplification to create a dual-phase sensitive phase-locked amplification detection circuit. These specific design ideas were tested using a weak signal, which passed through the preamplifier, secondary amplifier, and band-pass filter comprising the target channel for signal amplification and noise filtering. The effective signal amplitude is proportional to the inverse phase difference between the direct current (DC) signal and inversely proportional to the amplitude of the signal. Finally, the DC signal was passed through an analog-to-digital converter (ADC). The analog-to-digital converter (A/D) is used to collect and calculate the DC signal, enabling the detection of weak electrical signals. Simulation experiments demonstrated that the signal detection circuit has an amplitude error below 0.2% and a phase error below 0.5%. The phase-locked amplification circuit designed in this paper can effectively extract the tiny impedance change signals of the planar coil sensor probe with high sensitivity and good robustness.

A 2.41 ppm/°C bandgap voltage reference with second‐order curvature compensation

SummaryA current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV.