Analog-to-digital Research Articles

Model Updating and Assessment using Axial Strains for a Statically Determinate Truss Bridge

The safety of aging structures over the course of their service life is given by structural reliability. Additionally, there is a lack of techniques available for processing raw structural health monitoring (SHM) data in a way that makes it possible to validate and/or update structural reliability. Along with the diagnosis of structural anomaly using SHM techniques, the prognosis of structural condition is also an important aspect. Field-measured strain responses can be used as an indication of structural safety and provide information regarding the load-carrying capacity of the structure. Reliability assessment can be conducted only if a more accurate digital analogue is obtained for the actual bridge and when the structural responses can be predicted accurately. This paper validates a digital model of a real-life railway truss bridge. Pamban bridge is a century-old railway bridge having one track and four internally statically determinate truss leaves. Electrical strain gauges are instrumented to measure the axial strain responses in 84 out of 92 members of the bridge. Strain responses of 1072 train movements that traversed the bridge from 1st January 2021 to 14th July 2021 are recorded, and root mean square error (RMSE) between these field-measured strain responses and analytically computed strain responses from the digital model are estimated. The stationary trend of the time history of RMSE values depicts constant structural reliability. A technique is also proposed to forecast structural strain responses, which is validated with field-measured strain responses.

Cost-Effective Data Acquisition Systems for Advanced Structural Health Monitoring.

With the growing demand for infrastructure and transportation facilities, the need for advanced structural health monitoring (SHM) systems is critical. This study introduces two innovative, cost-effective, standalone, and open-source data acquisition devices designed to enhance SHM through the latest sensing technologies. The first device, termed CEDAS_acc, integrates the ADXL355 MEMS accelerometer with a RaspberryPi mini-computer, ideal for measuring strong ground motions and assessing structural modal properties during forced vibration tests and structural monitoring of mid-rise buildings. The second device, CEDAS_geo, incorporates the SM24 geophone sensor with a Raspberry Pi, designed for weak ground motion measurements, making it suitable for seismograph networks, seismological research, and early warning systems. Both devices function as acceleration/velocity Data Acquisition Systems (DAS) and standalone data loggers, featuring hardware components such as a single-board mini-computer, sensors, Analog-to-Digital Converters (ADCs), and micro-SD cards housed in protective casings. The CEDAS_acc includes a triaxial MEMS accelerometer with three ADCs, while the CEDAS_geo uses horizontal and vertical geophone elements with an ADC board. To validate these devices, rigorous tests were conducted. Offset Test, conducted by placing the sensor on a leveled flat surface in six orientations, demonstrating the accelerometer's ability to provide accurate measurements using gravity as a reference; Frequency Response Test, performed at the Gebze Technical University Earthquake and Structure Laboratory (GTU-ESL), comparing the devices' responses to the GURALP-5TDE reference sensor, with CEDAS_acc evaluated on a shaking table and CEDAS_geo's performance assessed using ambient vibration records; and Noise Test, executed in a low-noise rural area to determine the intrinsic noise of CEDAS_geo, showing its capability to capture vibrations lower than ambient noise levels. Further field tests were conducted on a 10-story reinforced concrete building in Gaziantep, Turkey, instrumented with 8 CEDAS_acc and 1 CEDAS_geo devices. The building's response to a magnitude 3.2 earthquake and ambient vibrations was analyzed, comparing results to the GURALP-5TDE reference sensors and demonstrating the devices' accuracy in capturing peak accelerations and modal frequencies with minimal deviations. The study also introduced the Record Analyzer (RECANA) web application for managing data analysis on CEDAS devices, supporting various data formats, and providing tools for filtering, calibrating, and exporting data. This comprehensive study presents valuable, practical solutions for SHM, enhancing accessibility, reliability, and efficiency in structural and seismic monitoring applications and offering robust alternatives to traditional, costlier systems.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

Design of a nano-scale optical 2-bit analog to digital converter based on artificial intelligence

A novel, to our knowledge, optical 2-bit analog to digital converter (ADC) plasmonic waveguide was proposed using a metal–insulator–metal (MIM) with a circular disk resonator. A mutual cooperation between the finite element method of COMSOL software and MATLAB with the aid of artificial intelligence (AI) presented by the multi-layer perceptron (MLP) has been proposed for implementing the main structure. The phase shift difference between the input and the control ports is the basic principle used to select the outcomes on the output port. The transmission threshold (Tthreshold) is selected to be 0.5, resonance wavelength is 1040 nm, and the footprint of the design is 1200×2500nm. Several criteria like full width at half maximum (FWHM), contrast ratio (CR), modulation depth (MD), insertion loss (IL), and curves covering a complete wavelength range from 800 to 2000 nm versus transmission value (Tv) are simulated to evaluate the plasmonic system performance. The FWHM is 17 nm, CR is equal to 10.8 dB, MD and IL are 98.17% and −1dB, respectively, and the quality factor (Q-factor) for a single segment of the design reached 61.17.

Input currents of CMOS SAR ADC in microcontroller, their measurement and behavior model from users point of view

The article introduces the possible issue of internal CMOS Successive Approximation Register microcontroller’s Analog-to-Digital Converters (ADC) input currents. It describes the nature of the ADC input current and its dependence on the sampling frequency but also explains the issue when the ADC input appears to the user as a voltage source. Methods for measurement of parameters such as input charge, residual voltage, and equivalent capacitance of sample-hold circuits are presented and used in the proposed simplified model of ADC input behavior. These parameters, which are not listed in the datasheets, if not respected in the data acquisition design, can adversely affect how the ADC is used when measuring signal sources with non-negligible internal resistance. The article also explains how to solve a voltage measurement on a source with high internal resistance even in a situation where, according to datasheets, it should already have limitations. If the microcontroller contains a dynamically switched multiplexer, it can lead to other consequences, such as changing the input current or residual voltage. The proposed simplified CMOS SAR ADC input behavior model in an MCU can help users in an MCU-based data acquisition system design.

A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study

In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving ENOB>3.83 bits, SFDR>28.7 dBc for fin≤1.75 GHz, with no missing codes and a low power consumption of Pdiss=3.1 mW/core.

Parallel photonic chip for nanosecond end-to-end image processing, transmission, and reconstruction

Image processing, transmission, and reconstruction constitute a major proportion of information technology. The rapid expansion of ubiquitous edge devices and data centers has led to substantial demands on the bandwidth and efficiency of image processing, transmission, and reconstruction. The frequent conversion of serial signals between the optical and electrical domains, coupled with the gradual saturation of electronic processors, has become the bottleneck of end-to-end machine vision. Here, we present an optical parallel computational array chip (OPCA chip) for end-to-end processing, transmission, and reconstruction of optical intensity images. By proposing constructive and destructive computing modes on the large-bandwidth resonant optical channels, a parallel computational model is constructed to implement end-to-end optical neural network computing. The OPCA chip features a measured response time of 6 ns and an optical bandwidth of at least 160 nm. Optical image processing can be efficiently executed with minimal energy consumption and latency, liberated from the need for frequent optical–electronic and analog–digital conversions. The proposed optical computational sensor opens the door to extremely high-speed processing, transmission, and reconstruction of visible contents with nanoseconds response time and terahertz bandwidth.

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

Predictors of young students’ school participation during the early days of COVID-19 remote learning

When the COVID-19 pandemic forced school closures in the U.S. in March 2020, children’s learning moved home and online, making school participation a challenge for many families, particularly those with low incomes. Although there is not a clear and agreed-upon digital analog for in-person school participation for young elementary students, existing research on young children’s school attendance and engagement in non-pandemic times suggests that family characteristics broadly recognized to shape child development (e.g., parental depressive symptoms, household chaos), children’s own characteristics (e.g., pre-COVID-19 academic skills, demographics), and logistical barriers with particular relevance to remote learning (e.g., internet access) may be determinants of remote learning participation. The current study explores the extent to which student participation during COVID-induced remote learning was predicted by family and child characteristics and logistical barriers by drawing on an existing study of diverse low-income students in Tulsa, OK who were in first grade when the pandemic emerged. We capitalize on unique, comprehensive, multi-informant data collected before and during COVID-19 to examine young children’s participation in remote learning while controlling for pre-existing differences that might otherwise be confounded with both COVID-related stressors and obstacles to remote learning participation. Both family characteristics (e.g., parent depression, household chaos, single mother) and logistical barriers (e.g., internet and device access) predicted children’s remote learning participation. Implications for school administrators and policymakers with a focus on preparation for future disasters that may once again force school closures − are discussed.

Group delay of a signal in the receiving path estimation of measuring devices with the use of the step response

The current parameters coordinate-time measuring instruments calibration methods of global navigation satellite systems are considered. For coordinate-time measuring instruments calibration in the process of their development and testing, the global navigation satellite systems signals simulators are used. However, the simulators also need a calibration procedure. Currently, there are various methods for ensuring the metrological characteristics of simulators, including their calibration using oscilloscope. However, this method has not only advantages, but also limitations related to the use of an oscilloscope. VNIIFTRI develops a new reference measuring device – the calibrator of the global navigation satellite systems simulator. Since the work of the calibrator is based on the same principles as the work of the navigation receiver and the calibrator determine the time delay of accepted signal from the calibrated simulator, it is extremely important to accurately evaluate the own group time delay of the calibrator by the reception circuit and develop the methodology of determining the determination this metrological characteristic. The schematic solutions used of creating a calibrator include digital blocks, such as digital-analog or analog-cyphrane converters. The purpose of the study is to evaluate the group time delay in the input circuit of the calibrator containing an analog-digital converter. Traditional group delay estimation methods using S-parameters are not suitable for this purpose because they cannot compare analog and digital signals. This article has developed an indirect method for assessing the grouping time delay in the calibrator input circuit. The method proposed by the authors determines the group time delay time in the reception of the calibrator according to the circuit transition characteristic. The method is verification and calibration of measuring equipment using the input and output signals with an analog-digital converting. Using the proposed method, the group time delay in the calibrator circuit containing an analog-digital converter is estimated. The results of studies are given by the proposed method of this parameter of circuits with various microwave devices (power splitter, circulator). The proposed method allows you to obtain accurate assessments of the frequency characteristics of the measuring devices circuits and normalize their metrological characteristics.

The influence of phase noise and nonlinear distortions of high-speed digital-to-analog converters on the parameters of digital communication systems

Problem statement. The trend in modern microwave electronics to transfer analog functions to the digital domain has led to the emergence and active use of high-speed digital-to-analog converters (DACs) in special operating modes in promising communication systems. However, optimization of power consumption and economic costs of signal generators (for example, through the use of simplified clock generators or by saving FPGA memory) leads to an increase in phase noise and nonlinear distortions in the output signal, which has a significant impact on the parameters of the communication system. Goal. Evaluation of phase noise and nonlinear distortions of signal generators based on high-speed digital-to-analog converters, as well as the study of their effect on the parameters of a digital communication system. Results. Expressions for estimating the spectral power density of phase noise of a signal generator based on a high-speed DAC are proposed. It is determined that the level of phase noise of the shaper is mainly determined by the noise of the clock generator. The jitter of the communication system was evaluated when using a surfactant generator and a PLL-based synthesizer as a clock generator. A mathematical model of the output signal of the shaper is proposed, taking into account nonlinear distortions caused by sampling, phase code truncation and amplitude quantization. A model of a communication system with multi-position quadrature amplitude modulation has been developed to evaluate parameters taking into account phase noise and nonlinear distortion of the shaper based on high-speed DACs. It is determined that the intrinsic phase noise of the signal generator leads to an increase in the probability of bit error (by about an order of magnitude compared to ideal formers). The use of surfactant generators as clock generators makes it possible to reduce the probability of bit errors of the communication system by 3-5 times compared with PLL-based synthesizers. Practical significance. It is shown that the displacement of points in the signal constellation is mainly influenced by nonlinear distortions of the output signal of high-speed DACs caused by truncation of the phase code, as well as incomplete suppression of spectral components located in the neighboring Nyquist zone. The proposed mathematical apparatus makes it possible to determine the optimal frequency ratios in the structure of the shaper, at which the lowest values of the displacement of the constellation points are achieved.

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

A hybrid SAR ADC with input range extension

—This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR) analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor units and a reference voltage VREF, it attains a ±1.875VREF input range and a resolution of 10.91 bits. The hybrid SAR ADC decomposes the capacitive digital-to-analog converter (CDAC) into an incremental CDAC and a binary-weighted CDAC. For input signals larger than 0.75 VREF, the incremental CDAC is used to reduce the net sampling charge by biasing its capacitor bottom plates on proper reference voltage to implement input range extension. Furthermore, the increment CDAC contributes to enhancing linearity. The input frequency limitation is theoretically analyzed in the paper. This design is implemented with a 180-nm CMOS technology and achieves a 10.47 effective number of bits (ENOB). It consumes 26.8 μW at 1 MS/s with a 1.8-V supply and occupies an area of 0.0118 mm2.

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

A 36-nW Electrocardiogram Anomaly Detector Based on a 1.5-bit Non-Feedback Delta Quantizer for Always-on Cardiac Monitoring.

An always-on electrocardiogram (ECG) anomaly detector (EAD) with ultra-low power (ULP) consumption is proposed for continuous cardiac monitoring applications. The detector is featured with a 1.5-bit non-feedback delta quantizer (DQ) based feature extractor, followed by a multiplier-less convolutional neural network (CNN) engine, which eliminates the traditional high-resolution analog-to-digital converter (ADC) in conventional signal processing systems. The DQ uses a computing-in-capacitor (CIC) subtractor to quantize the sample-to-sample difference of ECG signal into 1.5-bit ternary codes, which is insensitive to low-frequency baseline wandering. The subsequent event-driven classifier is composed of a low-complexity coarse detector and a systolic-array-based CNN engine for ECG anomaly detection. The DQ and the digital CNN are fabricated in 65-nm and 180-nm CMOS technology, respectively, and the two chips are integrated on board through wire bonding. The measured detection accuracy is 90.6% ∼ 91.3% when tested on the MIT-BIH arrhythmia database, identifying three different ECG anomalies. Operating at 1 V and 1.4 V power supplies for the DQ and the digital CNN, respectively, the measured long-term average power consumption of the core circuits is 36 nW, which makes the detector among those state-of-the-art always-on cardiac anomaly detection devices with the lowest power consumption.

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.

EMG Instrumentation Modeling and Feature Processing Based On Discrete Wavelet Transform

Electromyography (EMG) instrumentation is essential in generating electrical signals from skeletal muscles. EMG sensors are helpful in various cases requiring the detection of human muscle contractions, neuromuscular disorders, and rehabilitation. EMG instrumentation is divided into two parts, namely, the analogue part and the digital part. The EMG instrumentation design comprises a digital-to-analog converter (DAC), instrumentation amplifier, filter, and analog-to-digital converter (ADC). Meanwhile, in digital signal processing adopting the Discrete Wavelet Transform (DWT) method, frequency analysis using DWT has proven superior. It is used in various research and has exceptionally detailed coefficient features for classifying neuromuscular disease signals. Therefore, this research aims to design analogue and digital EMG instrumentation and identify features in the form of detailed coefficients. The data used are two Physionet signals from the anterior tibialis body with myopathy and neuropathy disorders. The results obtained for EMG analogue instrumentation provide the expected results until they reach the filter component stage. The resulting signal forms a block in the filter component, different from the initial EMG signal. Meanwhile, the DWT decomposition results are of the Daubechies4 wavelet type with the highest level 17, which has a high detail coefficient at low frequencies, high dilation and the result of a mixture of neuropathy and myopathy EMG signals, or in other words, at low energies, this result is by the DWT theorem. Determining the efficiency of the DWT detailed coefficient feature requires further study with the same signal subject. The DWT features obtained can then be developed for various needs in EMG signal recognition.