Analog Signal Processing Applications Research Articles

Current Conveyors: Classification, Structures and Applications

Current conveyors (CCs) are replacing op amps in almost all analog signal-processing applications. The current mode architecture of CCs is particularly suitable for low voltage and high frequency applications. CCs can easily be reconfigured into different current mode structure. The classification scheme, the structures and a number of analog applications of CCs are presented in this tutorial article. The structures described can be implemented in CMOS technology.

Differential-voltage attenuator based on floating-gate MOS transistors and its applications

In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The attenuator constructed by only two stacked identical FGMOS in saturation region, provides a voltage output proportional to the difference of the two input voltages. The advantages of this attenuator are the low supply operation, the rail-to-rail input range with small linearity error and the single-ended input processing. A very efficient technique to transform any circuit that requires only balanced inputs into the single-ended counterpart based on the attenuator, is proposed. Using this technique, a number of single-ended computational circuits are produced such as voltage squarer, four-quadrant multiplier, and vector summation circuit. The circuits can be fabricated in standard double-poly, double-metal CMOS technology and they are suitable for analogue signal processing and neural networks applications. SPICE simulation results using 2-/spl mu/m MIETEC CMOS process parameters demonstrate the feasibility and the accuracy of the circuits.

Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation.

Low-Voltage Analog Tripler Circuit

A new low-voltage CMOS tripler is presented in this paper. It is realized by the square-law characteristics of MOS transistors operating in saturation. The proposed circuit has been fabricated in a 0.8 μm CMOS process. Experimental results have been given to demonstrate the feasibility of the proposed circuit. It is expected to be useful in low-voltage analog signal-processing applications.

Novel CMOS wide-linear-range transconductance amplifier

A novel technique for linearizing long tail differential pairs is proposed. It is shown that the proposed linearized transconductor offers excellent linearity and exceptionally wide operating range, which makes it suitable for operating in analog signal processing applications. PSpice simulation results are given.

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with −3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a −3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.

Dual-input RC integrator and differentiator withtuneable time constants using current feedback amplifiers

A dual-input RC active integrator and a differentiator with tuneable time constants are described. They are suitable for analogue signal processing applications, and have been implemented using a commercially available current feedback amplifier. Experimental results confirm theoretical prediction.

Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors

A low-voltage BiCMOS four-quadrant multiplier using triode-region transistors is presented, this circuit has been fabricated in a 1.0 /spl mu/m BiCMOS process. Experimental results show that for a power supply of /spl plusmn/1.5 V, the linear range is over /spl plusmn/0.6 V with the linearity error of less than 2%. The total harmonic distortion is less than 2% with an input range up to /spl plusmn/0.6 V. The measured -3-dB bandwidth of this proposed BiCMOS multiplier is about 10 MHz. This circuit is expected to be useful in low-voltage analog signal-processing applications.

Analogue BiCMOS squarer and its applications

A BiCMOS squarer using active attenuators which has been fabricated in a 10 /spl mu/m BiCMOS process is presented. Experimental results show that the nonlinearity of the squarer can be kept below 2%, across the entire input voltage range of /spl plusmn/0.3 V. Its -3 dB bandwidth is measured to be /spl sim/1 MHz. Moreover, based on the proposed squarer circuits, a four-quadrant multiplier and a vector summation circuit have also been realised. The proposed circuits are expected to be useful in analogue signal processing applications.

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 μm BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured −3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 μW. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.

Class AB wide dynamic range bipolar differentialvoltage-to-current converter with constant transconductance

A new wide dynamic range, class AB, bipolar differential voltage-to-current converter (DVCC), which features a virtually constant transconductance (gm) over the useful dynamic range and is suitable for monolithic IC fabrication, is described. The new DVCC, which additionally provides fairly good DC-AC performance, is mainly intended for precision, high-speed analogue signal conditioning and processing applications and building blocks, such as fast settling operational amplifiers, fast settling front ends for analogue to digital converters and digital to analogue converters. Some SPICE simulation results are also reported, which demonstrate the effectiveness of the proposed technique.

High Linearity BiCMOS Multiplier/Transconductor Structures

A new wide-input range BiCMOS analog multiplier is proposed based on the triode and saturation region operation of the MOS transistors. The new circuit can also be reconfigured to operate as a versatile Operational Transconductance Amplifier, OTA, with independent current bias control for N stages. The novel design involves the use of attenuators at the input stage to boost the input linear range. It also utilizes a high output impedance subtractor setup at the output stage to obtain a single-ended output. The new circuit is characterized by its large input range, its high linearity and ability to operate at low voltages as well as high frequencies. HSPICE simulation results of the circuit, using the MOSIS 2 µm process parameters, resulted in an input range of ±4 V (±5 V supply), ±1.9 V (±3 V supply) and ±1 V (±2 V supply), with linearity error less than 0.5%. It’s usages in certain analog signal processing applications are also discussed.

Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs

A low-voltage four-quadrant multiplier using floating-gate MOSFETs is presented. This circuit has been implemented in a 0.8 µm double-poly double-metal CMOS process. Experimental results show that for a single power supply of 2.5 V, the total harmonic distortion is less than 1.4% with input range up to 1 VP-P. The modulation application of this multiplier can be operated over 20 MHz. Moreover, it can operate satisfactorily regardless of the transistor body connection. This circuit is expected to be useful in low-voltage analogue signal processing applications.

Low-voltage CMOS four-quadrant multiplier

A new CMOS four-quadrant multiplier that can operate from supply voltages of ±1.5 V is presented. This circuit was fabricated in a standard 0.8 µm single-poly double-metal CMOS process. Experimental results show that the nonlinearity can be kept <2% across the entire differential input voltage range of ±0.8 V. The total harmonic distortion is <2% with the differential input range up to ±0.8 V. The measured –3 dB bandwidth of this multiplier is ~5 MHz. It is expected to be useful in low-voltage analogue signal-processing applications.

A CMOS square-law vector summation circuit

A CMOS vector summation circuit using the square-law characteristics of MOS transistors in the saturation region is presented. Simulation and experimental results are given to verify the theoretical analyzes. Second-order effects such as mobility reduction and transistor mismatch are also investigated. The proposed circuits are expected to be useful in analog signal-processing applications.

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.

Analogue squarer and multiplier based on MOS square-lawcharacteristic

A simple CMOS squarer based on MOS square-law characteristic is presented. This circuit was fabricated in a 0.8 µm single-poly double-metal n-well CMOS process. Experimental results show that the nonlinearity of the squarer can be kept below 2% across the entire differential input voltage range of ±1 V. The total harmonic distortion is < 2% with the input range up to ±0.8 V. Moreover, a four-quadrant multiplier can be also realised using the proposed squarers. The proposed circuits are expected to be useful in analogue signal-processing applications.

Simple low-voltage high-speed high-linearity V-I converter with S/H for analog signal processing applications

This paper presents a simple, high-speed, high-linearity V-I converter that has a sample/hold (S/H) function and can be operated under low voltage supply. The converter can be used as the front end of current-mode signal processors. The proposed V-I converter circuit is comprised of a current copier and a small resistor that can be realized on chip by using polysilicon. The current copier employed in this implementation has a very small input impedance (/spl cong/50 /spl Omega/) and is settled within 0.1% in 15 ns under a power supply of 3.3 V. The high-linearity V-I conversion is achieved by using a small resistor (2 k/spl Omega/). Simulation results show that, with the transistor parameters of MOSIS 2 /spl mu/m CMOS technology, the converter achieves a small low-frequency THD (<-65 dB) at a sample rate of 25 MSamples/s, and consumes about 2.5 mW under a power supply of 3.3 V.

Design of high-speed high-accuracy current copiers for low-voltage analog signal processing applications

For high-accuracy current-mode circuits, their basic building blocks, current copiers, determine their speed and accuracy. A current copier suffers from two major error effects which are due to nonzero output conductance and clock feedthrough. This brief presents a simple current copier with a negative-feedback structure to alleviate the error due to nonzero output conductance, where the feedback amplifier is implemented by a bipolar inverter with high voltage gain and large bandwidth. This brief also presents the design constraints and trade-off for reducing the error due to the clock feedthrough. The PSPICE simulation results show that the copier achieves an accuracy of more than 10 b with a settling time within 6 ns for the input currents ranged from 0.5 to 3 mA, where a power supply of 3.3 V and a 2 /spl mu/m BiCMOS process are assumed. Thus, this current copier is well suited to the high-accuracy high-speed and low-voltage analog signal processing applications.

Low-voltage CMOS four-quadrant multiplier based on square-difference identity

A low-voltage CMOS four-quadrant multiplier based on the square-difference identity ([a + b]2 – a2 – b2) is presented. This circuit has been implemented in a 0.8 µm single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of ±1.5 V, the linear input range of this multiplier is within ±0.5 V with the linearity error less than 1%. The total harmonic distortion is less than 1% with input range up to ±0.5 V. The –3 dB bandwidth of this multiplier is measured to be about 1 MHz. Moreover, it can operate satisfactorily regardless of the transistor body connection. This circuit is expected to be useful in low-voltage analogue signal-processing applications.