Abstract
A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 μm BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured −3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 μW. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
