Analog Front-end Research Articles

An Energy-Efficient Small-Area Configurable Analog Front-End Interface for Diverse Biosignals Recording.

We introduce a fully integrated configurable analog front-end (CAFE) sensor intended to accommodate various types of bio-potential signals in this article. The proposed CAFE is composed of an AC-coupled chopper-stabilized amplifier to effectively reduce 1/f noise and an energy- and area-efficient tunable filter to tune this interface to the bandwidth of various specific signals of interest. A tunable active-pseudo-resistor is integrated into the amplifier's feedback to realize a reconfigurable high-pass cutoff frequency and enhance its linearity, while the filter is designed using a subthreshold-source-follower-based pseudo-RC (SSF-PRC) topology to attain the required super-low cutoff frequency without the need for extremely low biasing current sources. Implemented in TSMC 40 nm technology, the chip occupies an active area of 0.048 [Formula: see text] while consuming 2.47 μW DC power from a 1.2-V supply voltage. Measurement results indicate that the proposed design achieved a mid-band gain of 37 dB, with an integrated input-referred noise ( VIRN) of 1.7 μVrms within 1-260 Hz. The total harmonic distortion (THD) of the CAFE is below 1 % with a 2.4 m Vpp input signal. With a wide-range bandwidth adjustment capability, the proposed CAFE can be used in both wearable and implantable recording devices to acquire different bio-potential signals.

Design of analog front-end integrated circuit of tactile sensor for human-machine interface

—In this paper, a highly integrated analog front-end chip for sensor data acquisition and readout is designed, which is applied to a pressure-to-capacitance-conversion 16 × 16 tactile sensor array. In this design, a 16-channel capacitance-to-digital converter using a combination of op-amp-based Capacitance-Voltage Converter (CVC) and column-parallel Single-Slope Analog-to-Digital Converter (SS ADC) converters has been implemented, increasing the readout speed of the sensor array and saving the chip area. In addition, a sequence of scanning circuit suitable for the 16 × 16 array is proposed, so that the CVC and column-parallel SS ADCs are in a pipelined working mode, which further improves the speed of data conversion and readout. The integrated circuit (IC) is designed and taped out in a 0.18-μm CMOS process technology. The measurement results show that the chip can reach the capacitance detection range from 1 pF to 9.1 pF, and it achieves a detection accuracy of 9 fF under 10-bit ADC quantization. Under the clock frequency of 64 MHz, the refresh rate of the entire array is 3906 fps, and the overall power consumption of the front-end IC is 7.5 mW.

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

This paper presents a configurable analog front-end (AFE) for low-power neural recording systems that is capable of the current-to-voltage converter, programmable gain, ultra-high input impedance, low-noise, and wide bandwidth. A 6-channel AFE consisting of 6 1-channel AFEs is also introduced in this paper. The proposed AFE is designed on a 180nm CMOS process for low noise and operates over a wide frequency range of 0.5 Hz to 2.3 kHz with low input-referred noise of 1.8 μVrms and the maximal CMRR value of 180 dB. The power consumption is 8.5 μW per channel.

Photoplethysmography in Wearable Devices: A Comprehensive Review of Technological Advances, Current Challenges, and Future Directions

Photoplethysmography (PPG) is an affordable and straightforward optical technique used to detect changes in blood volume within tissue microvascular beds. PPG technology has found widespread application in commercial medical devices, enabling measurements of oxygen saturation, blood pressure, and cardiac output; the assessment of autonomic nerve function; and the diagnosis of peripheral vascular disease. Recently, the growing demand for non-invasive, portable, cost-effective technology, along with advancements in small semiconductor components, has led to the integration of PPG into various wrist-worn wearable devices. Multiple sensor structures have been proposed and, through appropriate signal processing and algorithmic application, these wearable devices can measure a range of health indicators during daily life. This paper begins by addressing the market status of wrist-worn wearable devices, followed by an explanation of the fundamental principles underlying light operation and its interaction with living tissue for PPG measurements. Moving on to technological advancements, the paper addresses the analog front end for the measurement of the PPG signal, sensor configurations with multiple light emitters and receivers, the minimum sampling rate required for low-power systems, and the measurement of stress, sleep, blood pressure, blood glucose, and activity using PPG signals. Several challenges in the field are also identified, including selecting the appropriate wavelength for the PPG sensor’s light source, developing low-power interpolation methods to extract high-resolution inter-beat intervals at a low sampling rate, and exploring the measurement of physiological phenomena using multi-wavelength PPG signals simultaneously collected at the same location. Lastly, the paper presents future research directions, which encompass the development of new, reliable parameters specific to wearable PPG devices and conducting studies in real-world scenarios, such as 24-h long-term measurements.

A Fast, Low-Jitter, and Low-Time-Walk Multi-Channel Front-End IC for Diamond and Silicon Radiation Detectors

This paper presents the design and implementation of a radiation-hardened analog front-end (AFE) integrated circuit (IC) developed for interfacing with solid state ionizing radiation detectors, providing accurate amplitude and time-of-arrival measurements. The AFE is designed for use in the Beam Conditions Monitor Prime (BCM’) of the ATLAS experiment at the Large Hadron Collider (LHC). The proposed AFE is comprised of four channels, allowing for re-configuration to operate as either a low-noise high-gain amplifier for beam luminosity measurements, or a high-linearity low-gain amplifier for beam abort functionality. Each of the AFE channels consists of a low noise trans-impedance amplifier (TIA) optimized for minimal jitter and amplitude noise, a second stage differential amplifier, followed by a fully differential Constant Fraction Discriminator (CFD) to provide an amplitude independent time pick-off with a wide dynamic range. The CFD utilizes a new all-pass filter delay topology and high-performance zero-crossing detector to minimize time-walk. The core of each AFE channel occupies an area of 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 65 nm CMOS technology and consumes 57 mW, including the drivers. The measured AFE chips achieve 1 ns pulse rise time, 130 electron baseline equivalent noise charge (ENC), and <25 ps RMS jitter at 1 fC input charge. To the authors’ best knowledge, this work demonstrates the lowest published time-walk of ±6 ps across 30 dB signal dynamic range. Furthermore, irradiated AFEs are shown to tolerate up to 225 Mrad total ionizing dose with no significant degradation in measured performance characteristics.

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces

This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4) receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory interfaces. The proposed PAM-4 decoding technique obviates the need for additional comparators and reference voltages that are required in conventional PAM-4 decoders. Similar to conventional non-return-to-zero (NRZ) receivers, the proposed PAM-4 receiver uses only one comparator by decoding the LSB through time-windowing the outputs of the comparator that is used to decide a most significant bit (MSB). Therefore, the additional power overhead from a power-hungry analog front-end (AFE) and high-speed clock buffers is minimized in the proposed PAM-4 receiver because it is proportional to the number of comparators. Accordingly, the proposed PAM-4 receiver can achieve superior energy efficiency. Furthermore, the elimination of the use of reference voltages reduces the hardware cost and design complexity. A prototype single-ended PAM-4 receiver was fabricated in a 28-nm CMOS technology. It occupies 0.008 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 0.34 pJ/bit at 25 Gb/s.

A Two-element Interferometer for Millimeter-wave Solar Flare Observations

In this paper, we present the design and implementation of a two-element interferometer operating in the millimeter-wave band (39.5–40 GHz) for observing solar radio emissions through nulling interference. The system is composed of two 50 cm aperture Cassegrain antennas installed on a common equatorial mount, with a separation of 230 wavelengths. The cross-correlation of the received signals effectively cancels out the quiet solar component of the high flux density (∼3000 sfu) that reduces the detection limit due to atmospheric fluctuations. The system performance is as follows: the noise factor of the analog front end in the observation band is less than 2.1 dB, system sensitivity is approximately 12.4 K (∼34 sfu) with an integration time constant of 0.1 ms (default), the frequency resolution is 153 kHz, and the dynamic range is ≥30 dB. Through actual testing, the nulling interferometer observes a quiet Sun with a low level of output fluctuations (up to 50 sfu) and has a significantly lower radiation flux variability (up to 190 sfu) than an equivalent single-antenna system, even under thick cloud cover. As a result, this new design can effectively improve observation sensitivity by reducing the impact of atmospheric and system fluctuations during observation.

A Low-Cost Measurement Methodology for LiDAR Receiver Integrated Circuits

This paper presents a test methodology to facilitate the measuring processes of LiDAR receiver ICs by avoiding the inherent walk error issue. In a typical LiDAR system, a costly laser diode driver emits narrow light pulses with fast rising edges, and the reflected pulses from targets enter an optical detector followed by an analog front-end (AFE) circuit. Then, the received signals pass through the cascaded amplifiers down to the time-to-digital converter (TDC) that can estimate the detection range. However, this relatively long signal journey leads to the significant decline of rising-edge slopes and the output pulse spreading, thus producing inherent walk errors in LiDAR receiver ICs. Compensation methods requiring complex algorithms and extra chip area have frequently been exploited to lessen the walk errors. In this paper, however, a simpler and lower-cost methodology is proposed to test LiDAR receiver ICs by employing a high-speed buffer and variable delay cells right before the TDC. With these circuits, both START and STOP pulses show very similar pulse shapes, thus effectively avoiding the walk error issue. Additionally, the time interval between two pulses is easily determined by varying the number of the delay cells. Test chips of the proposed receiver IC implemented in a 180-nm CMOS process successfully demonstrate easier and more accurate measurement results.

Optimizing Time Resolution Electronics for DMAPs

Depleted Monolithic Active Pixel Sensors (DMAPSs) are foreseen as an interesting choice for future high-energy physics experiments, mainly because of the reduced fabrication costs. However, they generally offer limited time resolution due to the stringent requirements of area and power consumption imposed by the targeted spatial resolution. This work describes a methodology to optimize the design of time-to-digital converter (TDC)-based timing electronics that takes advantage of the asymmetrical shape of the pulse at the output of the analog front-end (AFE). Following that methodology, a power and area efficient implementation fully compatible with the RD50-MPW3 solution is proposed. Simulation results show that the proposed solution offers a time resolution of 2.08 ns for a range of energies from 1000 e− to 20,000 e−, with minimum area and zero quiescent in-pixel power consumption.

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.

Tablet-Based Wearable Patch Sensor Design for Continuous Cardiovascular System Monitoring in Postoperative Settings

Meticulous monitoring for cardiovascular systems is important for postoperative patients in postanesthesia or the intensive care unit. The continuous auscultation of heart and lung sounds can provide a valuable information for patient safety. Although numerous research projects have proposed the design of continuous cardiopulmonary monitoring devices, they primarily focused on the auscultation of heart and lung sounds and mostly served as screening tools. However, there is a lack of devices that could continuously display and monitor the derived cardiopulmonary parameters. This study presents a novel approach to address this need by proposing a bedside monitoring system that utilizes a lightweight and wearable patch sensor for continuous cardiovascular system monitoring. The heart and lung sounds were collected using a chest stethoscope and microphones, and a developed adaptive noise cancellation algorithm was implemented to remove the background noise corrupted with those sounds. Additionally, a short-distance ECG signal was acquired using electrodes and a high precision analog front end. A high-speed processing microcontroller was used to allow real-time data acquisition, processing, and display. A dedicated tablet-based software was developed to display the acquired signal waveforms and the processed cardiovascular parameters. A significant contribution of this work is the seamless integration of continuous auscultation and ECG signal acquisition, thereby enabling the real-time monitoring of cardiovascular parameters. The wearability and lightweight design of the system were achieved through the use of rigid–flex PCBs, which ensured patient comfort and ease of use. The system provides a high-quality signal acquisition and real-time monitoring of the cardiovascular parameters, thus proving its potential as a health monitoring tool.

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA.

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

Embedded System for the Simultaneous Study of SAHS and Cardiac Arrhythmia

This paper presents a proposed embedded system for the simultaneous study of Sleep Apnea/Hypopnea Syndrome (SAHS) and related cardiac arrhythmias, which can affect about 1 billion people worldwide. Its objective is to become a tool to research the relational causes of these disruptions. It can record biomedical signals and vital parameters related to cardiac and respiratory activity commonly used in clinical practice. The system is designed to be used in sleep studies, providing greater comfort to users by integrating two devices into one. The proposed system is battery-powered and has Bluetooth wireless communication for remote studies. The design is based on specific electronic components such as Analog Front-End and System on Chips, and best-practice guidelines for PCB design were followed. A hybrid-scheduler was selected as software architecture to ensure the task execution at specific intervals. The systems signal quality recording sub-system was tested using a multiparametric simulator, commercial holter device and acquired real records. The results are similar to other works.

A Pitch-Matched Low-Noise Analog Front-End With Accurate Continuous Time-Gain Compensation for High-Density Ultrasound Transducer Arrays

This article presents a compact analog front-end (AFE) circuit for ultrasound receivers with linear-in-dB continuous gain control for time-gain compensation (TGC). The AFE consists of two variable-gain stages, both of which employ a novel complementary current-steering network (CCSN) as the interpolator to realize continuously variable gain. The first stage is a trans-impedance amplifier (TIA) with a hardware-sharing inverter-based input stage to save power and area. The TIA’s output couples capacitively to the second stage, which is a class-AB current amplifier (CA). The AFE is integrated into an application-specific integrated circuit (ASIC) in a 180-nm high-voltage BCD technology and assembled with a 100 -pitch PZT transducer array of 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 8 elements. Both electrical and acoustic measurements show that the AFE achieves a linear-in-dB gain error below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.4 dB within a 36-dB gain range, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> better than the prior art. Per channel, the AFE occupies 0.025 area, consumes 0.8 mW power, and achieves an input-referred noise density of 1.31 .

A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs

In this paper, an analog front-end (AFE) local-field potential (LFP) acquisition unit with real-time stimulation artifact removal is proposed and verified for closed-loop deep brain stimulation (DBS) applications. The proposed acquisition unit is called the synchronized sample-and-hold stimulation artifact blanking (SSAB) AFE LFP acquisition unit. Both right-leg-driven (RLD) circuit and monopolar electrode-tissue impedance (ETI) measurement circuit associated with the AFE amplifier are also proposed. During closed-loop stimulations, the artifact removal is realized through the SSAB-IPC by blanking the AR-CCIA with a clock synchronized to the stimulation-enable signal and holding the amplifier at its state before stimulation through a sample-and-hold operation. After stimulation, the acquisition unit can quickly recover from the holding state back to the LFP recording state to reduce the discontinuity in LFP recording. The proposed acquisition unit was fabricated in 0.18-um CMOS technology. With the RLD circuit, the measured CMRR is 124 – 145 dB in the signal bandwidth. The fabricated monopolar ETI measurement circuit has a measurement error less than 8.3% with an extra power consumption of 2.65 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W. The experimental results have shown that the proposed SSAB AFE LFP acquisition unit is feasible for the integration of SoCs in real-time closed-loop DBS systems for various applications.

A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC

Across the board, the performance of ADCs has been under increasing scrutiny because of the rapid growth of portable electronic devices and biomedical sensors. As part of the sensor’s long-term work, its power consumption should also be as low as possible. Sensors benefit from SAR ADCs’ small size and low power consumption, making them an ideal fit for ADCs. To overcome the limitations of accuracy and linearity of ADCs caused by manufacturing process deviations, a 12-bit, 1 MS/s low-power SAR ADC based on 180 nm CMOS technology is presented. The front-end analog calibration system ensures the ADC is at its best. The design also includes low fan-in SAR logic to reduce the capacitive load on the comparator and increase the comparison speed. The layout area is 0.3 mm2, approximately 30% less than conventional products of the same process.

Design and Implementation of an Orbitrap Mass Spectrometer Data Acquisition System for Atmospheric Molecule Identification

Orbitrap mass spectrometers have gained widespread popularity in ground-based environmental component analysis. However, their application in atmospheric exploration for space missions remains limited. Existing data acquisition solutions for Orbitrap instruments primarily rely on commercial systems and computer-based spectrum analysis. In this study, we developed a self-designed data acquisition solution specifically tailored for atmospheric molecule detection. The implementation involved directly integrating a spectrum analysis algorithm onto a field programmable gate array (FPGA), enabling miniaturization, real-time performance, and meeting the desired requirements. The system comprises signal conditioning circuits, analog-to-digital conversion (ADC) circuits, programmable logic circuits, and related software. These components facilitate real-time spectrum analysis and signal processing on hardware, enabling high-speed acquisition and analysis of signals generated by the Orbitrap. Experimental results demonstrate that the system can sample front-end analog signals at a rate of 25 MHz and differentiate signal spectra with an error margin of less than 7 kHz. This establishes the viability of the designed data acquisition system for atmospheric mass spectrometry analysis.

A Non-Newtonian liquid metal enabled enhanced electrography

Biopotential signals, like electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG), can help diagnose cardiological, musculoskeletal and neurological disorders. Dry silver/silver chloride (Ag/AgCl) electrodes are commonly used to obtain these signals. While a conductive hydrogel can be added to Ag/AgCl electrodes to improve the contact and adhesion between the electrode and the skin, dry electrodes are prone to movement. Considering that the conductive hydrogel dries over time, the use of these electrodes often creates an imbalanced skin-electrode impedance and a number of sensing issues in the front-end analogue circuit. This issue can be extended to several other electrode types that are commonly in use, in particular, for applications with a need for long-term wearable monitoring such as ambulatory epilepsy monitoring. Liquid metal alloys, such as eutectic gallium indium (EGaIn), can address key critical requirements around consistency and reliability but present challenges on low viscosity and the risk of leakage. To solve these problems, here, we demonstrate the use of a non-eutectic Ga–In alloy as a shear-thinning non-Newtonian fluid to offer superior performance to commercial hydrogel electrodes, dry electrodes, and conventional liquid metals for electrography measurements. This material has high viscosity when still and can flow like a liquid metal when sheared, preventing leakage while allowing the effective fabrication of electrodes. Moreover, the Ga–In alloy not only has good biocompatibility but also offers an outstanding skin-electrode interface, allowing for the long-term acquisition of high-quality biosignals. The presented Ga–In alloy is a superior alternative to conventional electrode materials for real-world electrography or bioimpedance measurement.

Performance Evaluation of E-Band Transmit-Receive Front-Ends Based on Characterization of Joint Effects of IQ Imbalance and Carrier Phase/Frequency Offset

A comprehensive approach for evaluating the performance of transmit–receive (TX–RX) analog front-ends as regards to the characterization of the joint effects of IQ imbalance and carrier phase/frequency offset is presented in this article. The study consists of a system model, a system-level (SL) simulation, and measurements. An SL discretization approach is implemented for the characterization of the joint effects of nonidealities. The approach uses SL simulation to assist in evaluating the measurement results. It also addresses the challenges associated with accurate performance estimation and assessment related to the nonidealities of the analog front-ends. The performance evaluation studies for the simulation and measurement are analyzed, considering recording time, evaluation period per frame, and averaging versus carrier frequency offset (CFO). The measurements are ensured with coherent and noncoherent local oscillator (LO) configurations concerning E-band simplex data transmission. The experimental studies are carried out based on bandwidth-and frequency-dependent performance evaluations. A correlation between the coherent and noncoherent LO configurations is reported in detail in terms of the evaluation of measured error vector magnitude (EVM) in the presence of the joint effects of IQ imbalance and carrier phase/frequency offset.

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.