Analog Front-end Circuit Research Articles

An expandable 36‐channel neural recording ASIC with modular digital pixel design technique

AbstractThis paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12‐bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9‐μV input referred noise (IRN), 10.8‐effective number of bits (ENOB), 37.8‐μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18‐μm CMOS process and validated by in‐vivo experiment on a lab mouse with a 36‐channel silicon‐based neural probe.

Low-power high-dynamic-range analog front-end for picosecond waveform sampling ASICs

This short communication presents an analog front-end (AFE) circuit used in the switched-capacitor array (SCA) for the waveform sampling ASIC. The idea to use in SCA-AFE native transistors which are common in today’s CMOS technologies offers a feasible solution to the issue of achieving picosecond time resolution with a low supply voltage. The circuit features a MOS capacitor and a source follower both of which are implemented with the native transistors, and a simple rail-to-rail comparator. A prototype PISTWAVE1 ASIC is designed in a 55 nm CMOS with a single 1.2 V supply voltage, the experimental results show the ASIC achieves a dynamic range of 0.1∼1.1 V, a 65.3 dB signal-to-noise ratio (SNR) with voltage calibration and a less than 10 ps time resolution. The overall power consumption is less than 10 mW/channel at a sampling rate of nearly 6 GS/s.

Microwave-sensor-node integrated into a short-range wireless sensor network

This paper presents the first microwave-sensor-node integrated into a short-range wireless sensor network based on ZigBee technology. The node includes an analog front-end circuit, a Frequency Modulated Continuous Wave generator, an Analog-to-Digital-Converter module, a transceiver, a power unit, a processing unit and a new one-port dielectric permittivity sensor which is able to measuring the separation of structural cracks by the reflection coefficient measured in microwave frequencies. The analog front-end is composed of a pair of power dividers, an isolator and a mixer. The dielectric permittivity sensor is based on a patch antenna of variable length. The processing unit and transceiver are implemented with an Arduino UNO and an XBee module respectively. Additionally, the methodology for data processing is presented and the results of the measurement of a synthetic crack are presented. The results show that the system was successfully implemented with a sensitivity of 0.07 GHz/mm, for an opening range of between 0 and 5 mm and for a frequency range ranging from 2.782 GHz to 3.131 GHz. It is important to mention that the measurement was done remotely, placing the sensor 3 m from the client PC.

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

Assessment of a Calibration-Free Method of Cuffless Blood Pressure Measurement: A Pilot Study.

We design an adaptive algorithm to detect the feature of the pulse wave, making it possible for two sensors to measure the local PWV in the radial artery at a short distance. Unlike the cuffless BPM that needs to use a regression model for calibration. We encapsulate the piezoelectric sensor material in a cavity and design an analog front-end circuit. This study used color ultrasound imaging equipment to measure radial arterial parameters, including the diameter and wall thickness, to aid the estimation of blood pressure (BP) using the Moens-Korteweg (MK) equation of hemodynamics. We compared the blood pressure estimated by the MK equation with the reference BP measured using an aneroid sphygmomanometer in a test group of 32 people, resulting in a mean difference of systolic BP of -0.63 mmHg, and a standard deviation of ±5.14 mmHg, a mean difference of mean arterial pressure (MAP) of 0.97 mmHg, with a standard deviation of ±3.54 mmHg, and a mean difference of diastolic BP of -1.14 mmHg, with a standard deviation of ±4.08 mmHg. This study has verified its compliance with ISO 81060-2. A new type of wearable continuous calibration-free BPM can replace the situation that requires the use of traditional ambulatory BPM and reduce patient discomfort. In this study can provide long-term continuous blood pressure monitoring in the hospital.

A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications

To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times 1.2$ </tex-math></inline-formula> mm2.

An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer

A low-power, low-noise, and high-bandwidth magnetometer that utilizes the magnetoimpedance (MI) element as a sensor head is presented. The MI element has a high sensitivity, and it can be implemented in the mm-scale through the MEMS process. The analog front-end (AFE) circuit of the magnetometer includes a digital calibration scheme that automatically enhances the loop gain of the system, resulting in high bandwidth and low-noise characteristics. The AFE circuit is designed based on a switched-capacitor (SC) approach, and its dedicated switching scheme can suppress the folded noise of an amplifier. A single-coil magnetic negative feedback architecture with correlated double sampling (CDS) enables to achieve a high dynamic range (DR) and stable passband gain in addition to simplifying the structure of the MI element. The AFE chip of the magnetometer is implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, and it achieves an 8-pT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz noise floor within a 31-kHz bandwidth and the DR of 96 dB, where the power consumption is 1.97 mW.

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail.The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ∼36mV/ke- when configured in High Gain Mode, and ∼20mV/ke- when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ∼68e-rms and ∼80e-rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ∼ 200ps time bin and the chip can deal with a maximum flux of ∼ 3.6MHzmm−2s−1. In photon counting mode, the chip can deal with up to ∼ 5GHzmm−2s−1.The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

A CMOS AFE With 37-nA rms Input-Referred Noise and Marked 96-dB Timing DR for Pulsed LiDAR

This paper presents an analog front-end (AFE) circuit with marked timing point for pulsed time-of-flight LiDAR that employs either sampling- or event-based timing approach. The proposed AFE adopts a dual-mode structure for its pre-amplifier which can be configured as a charge-sensitive amplifier (CSA) or a gated active load-assisted TIA (GALA-TIA), depending on the intensity of input current. As a result, both the sensitivity and dynamic range (DR) of the AFE have been effectively improved. In addition, the zero-crossing point of the output signal has been marked as the timing point with a built-in pulse shaper, which allows the back-end circuits of LiDAR receiver discriminate the timing conveniently and accurately. The measured input-referred RMS noise current of the proposed AFE is 37 nA. With dual-mode control, a linear output DR of 80 dB and a wide timing DR of 96 dB with walk error no more than ±160 ps have been achieved. For single-shot measurement application, only CSA mode was enabled and the pulse widths of saturated output signals have been measured to compensate the walk errors, which realized a timing DR of 78 dB with accuracy of ±150 ps. The averaged power consumption is 66 mW and the total silicon area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.79\times 0.42\,\,mm^{2}$ </tex-math></inline-formula> in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process.

A Fully-Analogue Light-to-Frequency Converter Circuit for Optical Sensing Applications

This paper reports on a novel analog front-end circuit designed to measure light intensity variations for portable/wearable and implantable sensor applications in different fields spanning from industry to biomedicine. The circuit is capable to follow variations of light intensity detected by a photodiode through the frequency modulation of a generated square wave output voltage signal. Therefore, the circuit can be seen as a light-to-frequency converter allowing for a quasi-digital output that can be measured by simple digital frequency meters so avoiding the use of transimpedance amplifiers and analog-to-digital converters. The proposed architecture of the analog front-end circuit has been designed at the transistor level in TSMC 180 nm standard CMOS technology in CADENCE Design System environment. The resulting characteristics and performances have been studied both theoretically and numerically. Moreover, a simplified version of the proposed circuit has been also implemented by using commercial off-the-shelf discrete components to study experimentally its main features. In this sense, the paper presents a series of experimental findings that fully validate the solution and prove its performances in terms of sensitivity and resolution as well as of time response to light intensity variations by using a laser operating in both steady-state and pulsed regimes. By varying the laser power up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.75~\mu \text{W}$ </tex-math></inline-formula> , the resulting circuit sensitivity and resolution are equal to 69.4 kHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and 432 pW, respectively. In general, these results combined with small power variations of lasers or LED devices, demonstrate that the proposed solution is suitable for low-voltage, low-power applications, as required in portable/wearable and implantable devices and systems.

Evolution of Bioamplifiers: From Vacuum Tubes to Highly Integrated Analog Front-Ends

The past century has seen the ongoing development of amplifiers for different electrophysiological signals to study the work of the heart. Since the vacuum tube era, engineers and designers of bioamplifiers for recording electrophysiological signals have been trying to achieve similar objectives: increasing the input impedance and common-mode rejection ratio, as well as reducing power consumption and the size of the bioamplifier. This review traces the evolution of bioamplifiers, starting from circuits on vacuum tubes and discrete transistors through circuits on operational and instrumental amplifiers, and to combined analog-digital solutions on analog front-end integrated circuits. Examples of circuits and their technical features are provided for each stage of the bioamplifier development. Special emphasis is placed on the review of modern analog front-end solutions for biopotential registration, including their generalized structural diagram and table of comparative characteristics. A detailed review of analog front-end circuit integration in various practical applications is provided, with examples of the latest achievements in the field of electrocardiogram, electroencephalogram, and electromyogram registration. The review concludes with key points and insights for the future development of the analog front-end concept applied to bioelectric signal registration.

Design and implementation of a signal processing ASIC for digital hearing aids

People with hearing loss can be benefited from assistive devices like hearing aids. This article presents the implementation of a signal processing chip for digital hearing aid applications. The functionality of the proposed design was tested in real-time using two field programmable gate arrays (FPGAs), one of them modeled as a hearing aid processor and the other as an external audio CODEC. The hearing aid processor contains an 18-band 1/3-octave ANSI S1.11 filter bank, which performs the audiogram compensation and a dynamic range compression algorithm to restrict the output signal to an acceptable loudness. The functionality of an external audio CODEC was replicated in the other FPGA to act as the analog front end circuit of a hearing aid. Serial Peripheral Interface (SPI) was used for communication between the two FPGAs. The SPI protocol was modified to make the hearing aid programmable through the data in line of the interface itself. The proposed hearing aid chip was implemented using standard cell based design flow with a 5x5 mm fixed die size intended to fit in a 48-pin package.

A Near-Sensor ECG Delineation and Arrhythmia Classification System

Cardiovascular disease (CVD) has become the leading cause of death worldwide. As a widely used method for diagnosing CVD, currently electrocardiogram (ECG) monitoring tends to be implemented in wearable devices. This paper presents the prototype an ECG delineation and arrhythmia classification (EDAC) system suitable for wearable ECG biosensors. The proposed EDAC system is intended to be implemented after the electrodes and the analog front-end circuit, and its aim is signal processing at a low hardware overhead. The system consists of a Delta-modulator-based analog-to-feature converter (AFC), a corresponding ECG detection/delineation/feature extraction algorithm (DDF), an automatic gain controller (AGC) block, and a patient-dependent linear kernel support vector machine (SVM) classifier. The AFC converts the input analog signal into digital data of the slope and slope variation of the input signal, which is then used for detecting QRS complexes, localizing the fiducial points, and extracting the feature vectors for each heartbeat in the DDF block. At the same time, the AGC sends out a gain control signal based on the detected QRS complex to adjust the gain of the front-end amplifier. Finally, the SVM block performs arrhythmia classification. The EDAC system performance is evaluated using the MIT-BIH arrhythmia database. The system achieves 0.88% (0.93%), 99.1% (99.1%), 87.0% (92.8%), 99.6% (99.5%), and 89.3% (92.9%) in F1 score, accuracy, sensitivity, specificity, and positive predictive values of the supraventricular ectopic beats (ventricular ectopic beats) versus normal heartbeats classification while maintaining a low power dissipation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.66~\mu \text{W}$ </tex-math></inline-formula> at 1 kHz operating frequency in the front-end AFC block). The proposed system is attractive to future wearable long-term ECG monitoring biosensors.

A 3 Giga Sample Per Second 14-bit Digital Receiver with 9 GHz Input Bandwidth for Solar Radio Observation

A new digital receiver with excellent performances has been designed and developed for solar radio observation, which can receive the radio signal from direct current (DC) to 9 GHz in the direct acquisition way. On the digital receiver, the analog-to-digital converter (ADC) with 14-bit, two input channels and 3 Giga Samples per second (Gsps) are used to acquire observed signal, and the field-programmable-gate-array chip XCKU115 acts as the processing module. The new digital receiver can be used to directly sample the solar radio signals of frequency under 9 GHz. When receiving the solar radio signal above 9 GHz, the new digital receiver can save 1–2 stages of frequency down-conversion, and effectively improve many indexes of the solar radio observation system, i.e., the time resolution, analog front-end circuit, weight and volume of the analog circuit system. Compared with the digital receiver with sampling rate below 1 Gsps used in existing solar radio telescope, the new digital receiver reduces the frequency switching times of large bandwidth, which is beneficial to improving the frequency and time resolutions. The ADC sampling resolution of 14 bits, providing a large dynamic range, is very beneficial to observing smaller solar eruptions. This receiver, which would be used in the solar radio observation system, well meets the latest requirements with the resolutions of time (≤1 ms) and frequency (≤0.5 MHz) for fine observation of radio signals.

(Invited) Carbon Nanotube Thin-Film Devices for Fully-Flexible Electronics

Since flexible electronic devices can come in close contact with soft human tissue, they are suitable as wearable sensor applications for long-term and non-invasive monitoring of biological signals in a wide range of fields such as medical/health care, sports, and so on. Previous flexible sensor systems require signal processing with either a remote terminal or rigid IC chips placed on the sensor device due to the lack of high-performance flexible analog-frontend circuit (AFE). The remote system may suffer from an incorporation of external noise. The use of rigid IC chips degrades the flexibility and durability of the wearable sensor. To realize a fully flexible sensor system, an AFE including amplifiers, filters, analog-digital converters is needed to be integrated as well as sensors monolithically on a flexible substrate. In this study, we have realized fully-flexible AFE with carbon nanotubes. The key circuit is a novel operational amplifier (op-amp) with a high gain and low operating voltage. The AFE can be operated at low-voltage and exhibits excellent stability and robustness against variability.

A Low-Computing-Complexity Touch Signal Detection Method and Analog Front-End Circuits Based on Cross-Correlation Technology for Large-Size Touch Panel.

This paper proposes a low-computing-complexity touch signal detection method and analog front-end (AFE) circuits based on cross-correlation technology for large mutual capacitance touch screen panels (TSPs). To solve the traditional touch signal detection method problem of lots of invalid data being sampled and processed in a large-size TSP, the proposed method only samples and processes the signals around the touch points rather than full-screen data to decrease the computing complexity and analog–digital convertor (ADC) acquisition number. Compared with the traditional method, the proposed touch points search algorithm complexity decreases from MN to M + nN where M, N, and n are the number of RX channels, TX channels, and touch points, respectively. The maximum ADC acquisition number of the proposed method decreases from MN to 18n. Based on the proposed touch signal detection method, the AFE circuits are designed by a 0.11 μm process. The proposed dual cross-correlation AFE achieves detection of the weak touch signal submerged in the large display panel noise. The average channel area and power consumption are decreased to 0.015 mm2 and 0.227 mW, respectively. The maximum frame rate is 384.6 Hz with 10 touch points. The proposed cross-correlation AFE achieves a high frame rate while reducing the die area and power consumption.

ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller.

Wearable biomedical systems allow doctors to continuously monitor their patients over longer periods, which is especially useful to detect rarely occurring events such as cardiac arrhythmias. Recent monitoring systems often embed signal processing capabilities to directly identify events and reduce the amount of data. This work is the first to document a complete beat-to-beat arrhythmia classification system implemented on a custom ultra-low-power microcontroller. It includes a single-channel analog front-end (AFE) circuit for electrocardiogram (ECG) signal acquisition, and a digital back-end (DBE) processor to execute the support vector machine (SVM) classification software with a Cortex-M4 CPU. The low-noise instrumentation amplifier in the AFE consumes 1.4 μW and has an input-referred noise of 0.9 μV RMS. The all-digital time-based ADC achieves 10-bit effective resolution over a 250-Hz bandwidth with an area of only 900 μm 2. The classification software reaches a sensitivity of 82.6% and 88.9% for supraventricular and ventricular arrhythmias respectively on the MIT-BIH arrhythmia database. The proposed system has been prototyped on the SleepRider SoC, a 28-nm fully-depleted silicon on insulator (FD-SOI) 3.1-mm 2 chip. It consumes 13.1 μW on average from a 1.8-V supply.

Analog Circuits Using Double-Gate Multilayer MoS2 Field-Effect Transistor for Sensor Applications

The advantages of novel double-gate (DG) multilayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors for analog circuit applications are presented. Such components are shown to be especially useful in signal-conditioning circuits in sensor instrumentation systems. The nearly symmetric DG device architecture can be exploited in the design of analog front-end circuits to mitigate the effect of flicker (1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> ) noise. Quantum mechanical calculations validated by comparisons with experimental data indicate that with active semiconductor layer thickness >2 monolayers (MLs), the sheet carrier density per gate is increased relative to single gate field-effect transistors (FETs) resulting in a lower noise figure. Calculated normalized noise spectral power densities for the single and DG thin-film transistors (TFTs) at the same gate bias clearly show that the DG devices have lower noise than the single gate devices. In sensors for low-frequency signals such as bio-signals, DG transistors allow convenient direct coupling of the signal through one gate, with the other gate available for mixing with a high-frequency signal and/or applying bias voltages without requiring large capacitors. Such circuits are well-suited for use with silicon CMOS technology using back-end-of-the-line (BEOL) fabrication methods.

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

In this paper, low-noise incremental delta–sigma analog front end (AFE) integrated circuit (IC) for capacitive microsensors is presented. A conventional capacitance-to-digital converter (CDC) mainly uses a multi-stage capacitive sensing amplified stage (CSA) and analog-to-digital converters. The multi-stage CSA is not suitable for application in various Internet of things (IoT) devices that require low power because the power consumption of the analog front-end circuit increases in proportion to the number of amplifiers and the chip area increases. So, the presented delta-sigma AFE can convert the capacitance changes to the digital codes directly. This structure can achieve a small active area and low power consumption. The delta–sigma AFE achieves low-noise and high linearity using a capacitor polarity swapping technique. The measured effective resolution is 16.2 bits, and the non-linearity is 0.05% full-scale output (FSO). The integrated circuit is implemented in a 0.18-µm standard CMOS process. All functional blocks, including the analog circuits (bandgap reference, voltage reference, and delta–sigma capacitance-to-digital converter) and digital block (accumulator and timing generator), are integrated on a chip. The proposed incremental delta–sigma AFE consumes 1.12 mW of power from a 3.3-V supply at a sampling frequency of 500 kHz and occupies a total active area of 0.42 mm2.

Analog Front-End: Circuit of Pulsar-Based Timing Synchronization for the WAMS

The front-end circuit used in the pulsar acquisition of the radio telescope determines the availability of the entire pulsar-based timing framework. However, it would be expensive and resource consuming to use a real radio telescope in the circuit design process. To address this issue, in this article, the hardware-in-the-loop simulation solution is proposed to generate, sample, and extract pulse signals in real time. The artificial pulse generation method is first proposed to generate the pulses that are close to real pulsar signals. Then, three analog front-end circuit architectures (AFCAs) are proposed to generate the analog pulses, including the superposition, attenuator, and attenuator-based superposition structures. The generated pulses are close to the real pulsar signal in shape, amplitude, and noise level. Next, a pulsar-based timing synchronization framework that can be used to improve the timing accuracy of the wide-area monitoring systems is developed to process the sampled data. Multiple experiments are conducted to verify the effectiveness of the analog front-end and the pulsar-based timing synchronization framework using the simulated pulse and real pulsar signals. The results demonstrated that the designed AFCAs can generate effective analog pulses, and is convenient and flexible.