Analog Computer Research Articles

Period finding and prime factorization using classical wave superposition

Prime factorization is a procedure of determining the prime factors of a given number N that requires super-polynomial time for conventional digital computers. Peter Shor developed a polynomial-time algorithm for quantum computers. Period finding is the key part of the algorithm, which is accomplished with the help of quantum superposition of states and quantum entanglement. The period finding can be also accomplished using classical wave superposition. In this study, we present experimental data obtained on a multi-port spin wave interferometer made of Y3Fe2(FeO4)3. Number 817 was factorized by a sequence of phase measurements. We also present the results of numerical modeling on the prime factorization of larger numbers 334597,1172693,3377663,and9363239. The results of numerical modeling reveal significant shortcomings of the period-based approach. The major problems are associated with an inability to predict the period of the modular function, significant overhead over classical digital computers in some cases, and phase accuracy requirements. We argue that the same problems are inherent in classical analog and quantum computers.

The analog computer: Beyond the museum artwork, a tool for studying linear and nonlinear systems

Analog computers have been a valuable resource for a time to solve linear as well as nonlinear differential equations before being superseded by digital computers. However, interest toward analog computing has not fully faded away. Though not competitive for accuracy or speed, analog computers have the important property of being true physical systems that can be made to behave according to a given equations set. This aspect makes analog computers interesting educational tools for hands-on work with real physical systems, where a number of effects, both linear and not linear, can easily be added at will (a feature not readily available in mechanical systems). This paper describes the implementation of a modular, very flexible, cheap, yet powerful analog computer, suitable for student laboratories. As examples of possible applications, a selection of linear and nonlinear oscillator models are described that can be used in the laboratory to introduce students to various nonlinear effects.

Review of Milestones in Analog and Digital Computing, 3rd ed by Herbert Bruderer

The book presents the major milestones of analog and digital computing. It was first published in German in 2015, followed by a significantly expanded two volume edition in 2018, and the third edition boasts added material and is now also available in English. The author exhaustively covers mechanical calculators, historical automata, and scientific instruments. In its detailed account of analog computing, this volume is surely unrivaled—the book discusses many groundbreaking analog devices, from the Antikythera (the first known astronomical calculator) to the Curta (the smallest mechanical parallel calculator), before venturing into the electronic era. The author not only compiles a historical guide to computing, he also offers detailed lists and tables that classify machines systematically: according to their function, their national origins, or according to where extant machines are collected or exhibited. The more recent past of digital computing is similarly more complex than it may at first appear. Who built the first computer? Who created the first stored-program calculator? What was the first compiler? It should be emphasized also that the author does not present a history of programming or of software—the accent remains firmly on hardware. Yet this book is addressed not only to the historians of technology or of science, archival curators or restoration experts, but also to anyone generally interested in the history of information processing and computer technology. The book is itself a milestone in computer history, and a much needed corrective to the tendency, both in industry and in academia, to see computing almost exclusively in terms of the near future. questions, beyond the superficial consolations of listicles and timelines. The information the author

Formulation and Emulation of Quantum-Inspired Dynamical Systems With Classical Analog Circuits.

Quantum dynamical systems are capable of powerful computation but are hard to emulate on digital computers. We show that four novel analog circuit parts can emulate the phase-coherent unitary dynamics of such systems. These four parts are: a Planck capacitance analogous to a neuronal membrane capacitance; a quantum admittance element, together with the Planck capacitance, analogous to a neuronal quadrature oscillator; a quantum transadmittance element analogous to a complex neuronal synapse; and a quantum transadmittance mixer element analogous to a complex neuronal synapse with resonant modulation. These parts may be emulated classically, with paired real-value voltages on paired Planck capacitances corresponding to the real and imaginary portions of a probability amplitude; and appropriate paired real-value currents onto these Planck capacitances corresponding to diagonal (admittance), off-diagonal (transadmittance), or controlled off-diagonal (transadmittance mixer) Hamiltonian energy terms. The superposition of 2n simultaneously phase-coherent and symmetric probability-voltage amplitudes with O(n) of these parts, in a tensor-product architecture enables analog emulation of the quantum Fourier transform (QFT). Implementation of our circuits on an analog integrated circuit in a 0.18 μm process yield experimental results consistent with mathematical theory and computer simulations for emulations of NMR, Josephson junction, and QFT dynamics. Our results suggest that linear oscillatory neuronal networks with pairs of complex subthreshold/nonspiking sine and cosine neurons that are coupled together via complex synapses to other such complex neurons can architect quantum-inspired computation with classical analog circuits. Thus, an analog-circuit mapping between quantum and neural computation, both of which exploit analog computation for powerful operation, can enable future synergies between these fields.

Dispersive and dissipative coupling of photon Bose-Einstein condensates

The synchronization of coherent states of light has long been an important subject of basic research and technology. Recently, a new concept for analog computers has emerged where this synchronization process can be exploited to solve computationally hard problems - potentially faster and more energy-efficient than what can be achieved with conventional computer technology today. The unit cell of such systems consists of two coherent centers that are coupled to one another in a controlled manner. Here, we experimentally characterize and analyze the synchronization process of two photon Bose-Einstein condensates, which are coupled to one another, either dispersively or dissipatively. We show that both types of coupling are robust against a detuning of the condensate frequencies and show similar time constants in establishing mutual coherence. Significant differences between these couplings arise in the behaviour of the condensate populations under imbalanced optical pumping. The combination of these two types of coupling extends the class of physical models that can be investigated using analog simulations.

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices

On-device embedded artificial intelligence prefers the adaptive learning capability when deployed in the field, and thus in situ training is required. The compute-in-memory approach, which exploits the analog computation within the memory array, is a promising solution for deep neural network (DNN) on-chip acceleration. Emerging non-volatile memories are of great interest, serving as analog synapses due to their multilevel programmability. However, the asymmetry and nonlinearity in the conductance tuning remain grand challenges for achieving high in situ training accuracy. In addition, analog-to-digital converters at the edge of the memory array introduce quantization errors. In this work, we present an algorithm-hardware co-optimization to overcome these challenges. We incorporate the device/circuit non-ideal effects into the DNN propagation and weight update steps. By introducing the adaptive “momentum” in the weight update rule, in situ training accuracy on CIFAR-10 could approach its software baseline even under severe asymmetry/nonlinearity and analog-to-digital converter quantization error. The hardware performance of the on-chip training architecture and the overhead for adding “momentum” are also evaluated. By optimizing the backpropagation dataflow, 23.59 TOPS/W training energy efficiency (12× improvement compared to naïve dataflow) is achieved. The circuits that handle “momentum” introduce only 4.2% energy overhead. Our results show great potential and more relaxed requirements that enable emerging non-volatile memories for DNN acceleration on the embedded artificial intelligence platforms.

Nonlocal Scatterer for Compact Wave-Based Analog Computing.

Analog computing based on wave interactions with metamaterials has been raising significant interest as a low-energy, ultrafast platform to process large amounts of data. Engineered materials can be tailored to impart mathematical operations of choice on the spatial distribution of the impinging signals, but they also require extended footprints and precise large-area fabrication, which may hinder their practical applicability. Here we show that the nonlocal response of a compact scatterer can be engineered to impart operations of choice on arbitrary impinging waves, and even to solve integro-differential equations, whose solution is observed in the scattered fields. The lack of strongly resonant phenomena makes the response robust, and the compact nature opens to scalability and cascading of these processes, paving the way to efficient, compact analog computers based on engineered microstructures.

Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing.

In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS2) and ambipolar (MoTe2) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.

Computing-in-Memory with Thin-Film-Transistors: Challenges and Opportunities

Abstract Thin-film transistor (TFT) has attracted enormous interests recently for its great potential in a wide range of edge computing applications, benefitting from its large-area low-cost flexible fabrications, and well integration with sensors and displays. With the support of in-situ processing of sensor data, TFT-based edge systems show their advantages in large-scale dense sensing with real-time energy-efficient processing and interaction, and more excitingly, it provides the opportunity of eliminating the massive data transfer to the cloud servers. However, the design of high-performance processing modules based on TFT is difficult, due to large device variation, poor stability, and low mobility. Computing-in-memory (CiM), which has been proposed recently as a high-efficiency high-parallelism computing approach, is expected to improve the capacity of TFT-based edge computing systems. In this survey, various recent works on TFT-based CiM have been summarized, showing the superiority to conventional processing flow by efficient in-memory analog computation with mitigation of data transfer, and reduced ADC usage for sensor data. With both opportunities and challenges, the design space and trend of TFT-based CiM to be explored are then described. Finally, further development and co-optimization from device to system are discussed for flourishing of the next-generation intelligent TFT-based edge system.

Flexible computational photodetectors for self-powered activity sensing

Conventional vision-based systems, such as cameras, have demonstrated their enormous versatility in sensing human activities and developing interactive environments. However, these systems have long been criticized for incurring privacy, power, and latency issues due to their underlying structure of pixel-wise analog signal acquisition, computation, and communication. In this research, we overcome these limitations by introducing in-sensor analog computation through the distribution of interconnected photodetectors in space, having a weighted responsivity, to create what we call a computational photodetector. Computational photodetectors can be used to extract mid-level vision features as a single continuous analog signal measured via a two-pin connection. We develop computational photodetectors using thin and flexible low-noise organic photodiode arrays coupled with a self-powered wireless system to demonstrate a set of designs that capture position, orientation, direction, speed, and identification information, in a range of applications from explicit interactions on everyday surfaces to implicit activity detection.

Flexible and Stretchable Memristive Arrays for in-Memory Computing

With the tremendous progress of Internet of Things (IoT) and artificial intelligence (AI) technologies, the demand for flexible and stretchable electronic systems is rapidly increasing. As the vital component of a system, existing computing units are usually rigid and brittle, which are incompatible with flexible and stretchable electronics. Emerging memristive devices with flexibility and stretchability as well as direct processing-in-memory ability are promising candidates to perform data computing in flexible and stretchable electronics. To execute the in-memory computing paradigm including digital and analogue computing, the array configuration of memristive devices is usually required. Herein, the recent progress on flexible and stretchable memristive arrays for in-memory computing is reviewed. The common materials used for flexible memristive arrays, including inorganic, organic and two-dimensional (2D) materials, will be highlighted, and effective strategies used for stretchable memristive arrays, including material innovation and structural design, will be discussed in detail. The current challenges and future perspectives of the in-memory computing utilizing flexible and stretchable memristive arrays are presented. These efforts aim to accelerate the development of flexible and stretchable memristive arrays for data computing in advanced intelligent systems, such as electronic skin, soft robotics, and wearable devices.

Simulation of Low Power Self-Selective Memristive Neural Networks for in situ Digital and Analogue Artificial Neural Network Applications

Self-selective memory devices are considered promising candidates for suppressing the undesired sneak path currents that appear within crossbar memory structures and compromise their performance during the write and read operations. Along these lines, in this work we present forming free SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{\mathbf{2}}$</tex-math></inline-formula> -based resistive devices with inherent self-selection and self-compliance properties. The devices can operate in dual mode, since they can perform volatile threshold switching and non-volatile bipolar resistive behavior by regulating the external voltage amplitude. Interestingly, the devices exhibit low operating voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 260 – 360 mV) and quick response time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 100 ns). A comprehensive model is then developed in order to interpret this unique feature and provide valuable insights into the underlying physical mechanisms. Additionally, self-activated neural networks are theoretically investigated by performing in-situ digital and analog computations, whereas the calculated outcomes are compared with traditional neural networks with transistors as selecting elements. More specifically, a logic NAND gate and supervised learning upon the MNIST dataset is performed, while the proposed neural network architecture is tuned differently according to the application. Notably, the acquired results are comparable with the respective data where selectors have been employed, indicating the promising aspects of the proposed memristive devices. Moreover, a thorough analysis is carried out regarding the correlation between the device's linearity and the recognition's accuracy score, offering valuable insights. The proposed architecture paves the way for the development of energy-efficient artificial neural network computing architectures with tunable properties.

Time-Dependent Landau-Ginzburg Equation-Based Ferroelectric Tunnel Junction Modeling With Dynamic Response and Multi-Domain Characteristics

Overcoming the drawbacks of the existing ferroelectric tunnel junction (FTJ) models which ignore the dynamic or multi-domain switching behaviors, we develop a more comprehensive FTJ model by combining the Time-Dependent Landau-Ginzburg (TDLG) equations to solve the multi-domain dynamic switching of ferroelectric layer and the Non-Equilibrium Green Function (NEGF) to solve the tunneling current. The model successfully reproduces the experimental results of our fabricated metal-ferroelectrics-insulator-semiconductor (MFIS) FTJ. This model empowers us to predict both the dynamic and multi-state switching of FTJ, showing its promise for applications in the high-density data storage and analog computing.

A Software-Circuit-Device Co-Optimization Framework for Neuromorphic Inference Circuits

Neuromorphic circuits, which usually use analog computation for vector-matrix multiplication (VMM) in neural networks (NN), are promising machine learning accelerators with much lower latency and power consumption than digital ones. Analog computation is expected to have a more efficient design space than digital computation since the signals are not digitized. Therefore, it is very suitable for Internet-of-Thing (IoT) applications that require ultra-low power consumption at a low cost. For IoT applications, sometimes it is also desirable to eliminate the digital circuits (such as adders, registers, shifters, multiplexers, and Analog-to-Digital Converters) between the VMM arrays to further reduce the power consumption. However, the optimization of a purely analog circuit is more difficult and requires full SPICE circuit simulations. In this paper, we present a software-circuit-device co-optimization framework using a python wrapper for automatic full circuit SPICE simulation and analysis for neuromorphic circuits. This framework allows users to experiment with how the NN design (software) affects the performance of the hardware neuromorphic circuits. It takes Verilog-A or SPICE models from calibrations or PDK in various technologies and emerging memories (such as ReRAM) without further calibration (unlike using behavior models). We show that the simulation time is reasonable even with hundreds of thousands of synapses under limited computation resources. Using ReRAM and a 45nm generic technology as an example, the effects of feedback network and OpAmp design, software ML architecture, and input data accuracy on the inference accuracy are studied.

A Survey on Technologies Which Make Bitcoin Greener or More Justified

According to recent estimates, one bitcoin transaction consumes as much energy as 1.5 million Visa transactions. Why is bitcoin using so much energy? Most of the energy is used during the bitcoin mining process, which serves at least two significant purposes: a) distributing new cryptocurrency coins to the cryptoeconomy and b) securing the Bitcoin blockchain ledger. In reality, the comparison of bitcoin transactions to Visa transactions is not that simple. The amount of transactions in the Bitcoin network is not directly connected to the amount of bitcoin mining power nor the energy consumption of those mining devices; for example, it is possible to multiply the number of bitcoin transactions per second without increasing the mining power and the energy consumption. Bitcoin is not only &#x201C;digital money for hackers&#x201D;. It has very promising future potential as a global reserve currency and a method to make the World Wide Web (WWW) immune to cyberattacks such as the Distributed Denial-of-Service attacks. This survey approached cryptocurrencies&#x2019; various technological and environmental issues from many different perspectives. To make various cryptocurrencies, including bitcoin (BTC) and ether (ETH), greener and more justified, what technological solutions do we have? We found that cryptocurrency mining might be cleaner than is generally expected. There is also a plan to make a vast renewable energy source available by combining Ocean Thermal Energy Conversion and Bitcoin mining. There are plans to use unconventional computing methods (quantum computing, reversible computing, ternary computing, optical computing, analog computing) to solve some of the issues regarding the vast energy consumption of conventional computing (including cryptocurrency mining). We think using spare computing cycles for grid computing efforts is justified. For example, there are billions of smartphones in the world. Many smartphones are being recharged every day. If this daily recharging period of twenty to sixty minutes would be used for grid computing, for example, finding new cures to cancer, it would probably be a significant breakthrough for medical research simulations. We call cryptocurrency communities to research and develop grid computing and unconventional computing methods for the most significant cryptocurrencies: bitcoin (BTC) and ether (ETH).

Metasurface-Based Optical Analog Computing: From Fundamentals to Applications

With unprecedented growth in data information over the past few decades, it is critically important to seek a faster and more efficient method to simplify data processing. In recent years, optical analog computing provides an available way due to its large capacity, energy saving, and high efficiency. Metasurfaces, as 2-dimensional artificial nanostructures, have shown an extraordinary ability for controlling light and paving a pathway toward all-optical analog computing. In this brief review, we discuss the latest development in metasurface-based optical analog computing. Theoretical fundamentals and experimental demonstrations of optical analog computing for resolving a variety of mathematical problems have been reviewed, including differential operation, convolution operation, and Fourier transformation. Finally, a brief introduction of emerging applications in microscopy imaging, quantum imaging, and holographic imaging is presented.

MIPSIMO: A Multi-Input Piezo-Adaptive Single-Inductor Multi-Output Energy Harvester Achieving Using a Shared Inductor With an Integrated Analog Computer Achieving 95% MPPT Efficiency

This paper presents a multi-input piezo-adaptive single-inductor multi-output (MIPSIMO) architecture that harvests energy from up to three inputs while regulating up to three loads plus a battery all in a single power stage. The proposed power management unit performs load domain inductor switching to reduce switching losses by 3x and allows recycling of excess energy back to the battery for decoupled single-stage regulation, all while utilizing an adaptive ON-time PFM control method during battery utilization to free up inductor cycles as much as possible for harvesting. The proposed architecture implements a technique that performs multi-phase piezoelectric harvesting (PEH) charge flipping (CF) using the single shared inductor from the power stage together with four flying capacitors that reduce the required inductor size by 8x while achieving 90% flipping efficiency. In addition, a fully-integrated power-extraction analog computer is employed to enable real-time hill-climbing MPPT compatible with PEH sources. Fabricated in 180nm, the analog computer achieves a MPPT efficiency of 95% and the converter supports power range of 6μW to 60mW, and achieves a peak efficiency of 87%.

Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing

This work demonstrates a programmable in-memory-computing (IMC) inference accelerator for scalable execution of neural network (NN) models, leveraging a high-signal-to-noise ratio (SNR) capacitor-based analog technology. IMC accelerates computations and reduces memory accessing for matrix-vector multiplies (MVMs), which dominate in NNs. The accelerator architecture focuses on scalable execution, addressing the overheads of state swapping and the challenges of maintaining high utilization across highly dense and parallel hardware. The architecture is based on a configurable on-chip network (OCN) and scalable array of cores, which integrate mixed-signal IMC with programmable near-memory single-instruction multiple-data (SIMD) digital computing, configurable buffering, and programmable control. The cores enable flexible NN execution mappings that exploit data- and pipeline-parallelism to address utilization and efficiency across models. A prototype is presented, incorporating a <inline-formula> <tex-math notation="LaTeX">$4 \times 4$ </tex-math></inline-formula> array of cores demonstrated in 16 nm CMOS, achieving peak multiply-accumulate (MAC)-level throughput of 3 TOPS and peak MAC-level energy efficiency of 30 TOPS/W, both for 8-b operations. The measured results shows high accuracy of the analog computations, matching bit-true simulations. This enables the abstractions required for robust and scalable architectural and software integration. Developed software libraries and NN-mapping tools are used to demonstrate CIFAR-10 and ImageNet classification, with an 11-layer CNN and ResNet-50, respectively, achieving accuracy, throughput, and energy efficiency of 91.51&#x0025; and 73.33&#x0025;, 7815 and 581 image/s, 51.5 k and 3.0 k image/s/W, with 4-b weights and activations.

Non-volatile memory based in-memory computing technology

By integrating the storage and computing functions on the fundamental elements, computing in-memory (CIM) technology is widely considered as a novel computational paradigm that can break the bottleneck of Von Neumann architecture. Nonvolatile memory device is an appropriate hardware implementation approach of CIM, which possess significantly advantages, such as excellent scalability, low consumption, and versatility. In this paper, first we introduce the basic concept of CIM, including the technical background and technical characteristics. Then, we review the traditional and novel nonvolatile memory devices, flash and resistive random access memory (RRAM), used in non-volatile based computing in-memory (nvCIM) system. After that, we explain the operation modes of nvCIM: in-memory analog computing and in-memory digital computing. In addition, the applications of nvCIM are also discussed, including deep learning accelerator, neuromorphic computing, and stateful logic. Finally, we summarize the current research advances in nvCIM and provide an outlook on possible research directions in the future.

On the Accuracy of Analog Neural Network Inference Accelerators

Specialized accelerators have recently garnered attention as a method to reduce the power consumption of neural network inference. A promising category of accelerators utilizes nonvolatile memory arrays to both store weights and perform $\textit{in situ}$ analog computation inside the array. While prior work has explored the design space of analog accelerators to optimize performance and energy efficiency, there is seldom a rigorous evaluation of the accuracy of these accelerators. This work shows how architectural design decisions, particularly in mapping neural network parameters to analog memory cells, influence inference accuracy. When evaluated using ResNet50 on ImageNet, the resilience of the system to analog non-idealities - cell programming errors, analog-to-digital converter resolution, and array parasitic resistances - all improve when analog quantities in the hardware are made proportional to the weights in the network. Moreover, contrary to the assumptions of prior work, nearly equivalent resilience to cell imprecision can be achieved by fully storing weights as analog quantities, rather than spreading weight bits across multiple devices, often referred to as bit slicing. By exploiting proportionality, analog system designers have the freedom to match the precision of the hardware to the needs of the algorithm, rather than attempting to guarantee the same level of precision in the intermediate results as an equivalent digital accelerator. This ultimately results in an analog accelerator that is more accurate, more robust to analog errors, and more energy-efficient.