Simulation of Low Power Self-Selective Memristive Neural Networks for in situ Digital and Analogue Artificial Neural Network Applications

Abstract

Self-selective memory devices are considered promising candidates for suppressing the undesired sneak path currents that appear within crossbar memory structures and compromise their performance during the write and read operations. Along these lines, in this work we present forming free SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{\mathbf{2}}$</tex-math></inline-formula> -based resistive devices with inherent self-selection and self-compliance properties. The devices can operate in dual mode, since they can perform volatile threshold switching and non-volatile bipolar resistive behavior by regulating the external voltage amplitude. Interestingly, the devices exhibit low operating voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 260 – 360 mV) and quick response time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 100 ns). A comprehensive model is then developed in order to interpret this unique feature and provide valuable insights into the underlying physical mechanisms. Additionally, self-activated neural networks are theoretically investigated by performing in-situ digital and analog computations, whereas the calculated outcomes are compared with traditional neural networks with transistors as selecting elements. More specifically, a logic NAND gate and supervised learning upon the MNIST dataset is performed, while the proposed neural network architecture is tuned differently according to the application. Notably, the acquired results are comparable with the respective data where selectors have been employed, indicating the promising aspects of the proposed memristive devices. Moreover, a thorough analysis is carried out regarding the correlation between the device's linearity and the recognition's accuracy score, offering valuable insights. The proposed architecture paves the way for the development of energy-efficient artificial neural network computing architectures with tunable properties.