Amplifier Structure Research Articles

An Unequally Spaced Multi-Tone Load–Pull Characterization Technique for Simultaneous Linearity and Efficiency Assessment of RF Power Devices

This paper presents an innovative experimental method for microwave power devices linearity characterization, based on a carefully designed multi-tone signal. Measurements working deeper into the understanding of in-band (IB) signal-to-noise characterization of nonlinear devices are presented. The test signal used in this paper is based on an unequally spaced multi-tone (USMT) signal, which is a tailored stimulus signal with flexible statistics. Its originality stands in its inherent property of allowing signal and intermodulation (IM) distortion separation to facilitate the derivation of the IB signal-to-noise ratio or linearity degradation, without assuming any specific modulation format. For the first time, this paper reports measurements with small $\Delta _{f}$ frequency arrangement using an USMT signal to investigate low frequencies (LFs) parasitic effect on the current and the linearity. Furthermore, this test bench allows to analyze together LF phenomena (“trapping effect”, memory effect, etc.) and high-frequency phenomena under large-signal condition with a telecom like signal. Smith chart load–pull linearity contours under wideband USMT test signals are reported for the first time. This provides a new tool to check system-level design specifications and to optimize radio frequency (RF) power amplifier structures with modulated signals. The measurements were performed using a GaN high-electron-mobility transistors (HEMT) 3-W transistor.

A compact power-efficient 0.5 V fully differential difference amplifier

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

Multipass active stretcher with large chirp for high-flux ultra-intense lasers.

We demonstrate a novel active multipass stretcher that can deliver pulses with large chirp, adjustable chirped pulse duration, and great beam quality for a high-flux chirped-pulse amplification system. The stretcher is based on a Martinez-type stretcher and a regenerative amplifier structure, and the laser pulses can be amplified while they are stretched in the cavity. By controlling the round trip of the pulses running in the cavity, chirped pulses with more than 10ns, even scaling to 30ns, pulse duration and 20nm bandwidth can be obtained very easily, which indicates a chirp rate of 0.5ns/nm at 1053nm central wavelength. Chirped pulses with several millijoules energy can be delivered with an Nd:glass-based intracavity amplifier used to compensate the losses. Benefited by the advantage of regenerative structure, the output pulses have excellent beam quality with M2 of 1.1. Finally, the chirped pulses from this novel stretcher are compressed to 1.13 times the Fourier transform limit. With these advantages, this novel multipass active stretcher is significant for ultra-intense laser systems, especially for high-flux and high-energy 100 petawatt lasers.

3 kW narrow-linewidth all-fiber amplifier with near diffraction limited beam quality

A theoretical model is established to simulate the stimulated Brillouin scattering (SBS) effect in fiber amplifiers using white noise signal (WNS) phase-modulated seed. Based on the theoretical model, the influences of amplifier structure and cut-off frequency of WNS on SBS threshold are discussed in detail. Through theoretical analysis, optimized amplifier structure and phase modulation signal are achieved to suppress SBS, and a fiber laser based on a main oscillator power amplifier with counter-pumped scheme is established. The oscillator, with 3 dB spectral linewidth of 48 GHz, is produced by a WNS phase-modulated single-frequency seed. The amplifier uses a 915 nm diode laser pump and 25/400 Yb-doped optical fiber. The output power reaches 3.02 kW at 1064 nm, with 3 dB root-mean-square linewidth of 48 GHz. Amplified quality is obtained with M, M at maximum power.

A high-precision and high-linearity readout integrated circuit for infrared focal plane array applications

This paper proposes a readout integrated circuit (ROIC) with high precision and high linearity based on the standard capacitive transimpedance amplifier (CTIA) structure. A high-swing cascode current mirror is introduced, which can restrain the influence of the front-end unstable voltage on the integrating unit. Also, the high-swing cascode current mirror can reduce the influence of the integral nonlinear error caused by the finite gain of the amplifier on the bias point, which will significantly increase the linearity and reduced the nonlinear error of the output. Moreover, buffered direct injection method is adopted in the bias circuit in order to ensure the bias point stability and reduce the non-uniformity. A 4 × 2 experimental chip have been fabricated by adopting AMS 0.35 μm CMOS process. The simulation and experimental results demonstrate the ROIC with the features of high linearity, high injection efficiency, stable bias point and low noise, which is suitable for high performance applications.

Analysis of Simple Half-Shared Transimpedance Amplifier for Picoampere Biosensor Measurements.

High-throughput recordings of small current are becoming more common in biosensor applications, including in vivo dopamine measurements, single-cell electrophysiology, photoplethysmography, pulse oximetry, and nanopore recordings. Thus, a highly scalable transimpedance amplifier design is in demand. Half-shared amplifier design is one way to improve the scalability by sharing the non-inverting side of the operational amplifier design for many inverting halves. This method reduces silicon area and power by nearly half compared to using independent operational amplifiers. In this paper, we analyze the scalability of a simple half-shared amplifier structure while investigating the tradeoff of increasing the number of inverting half amplifiers sharing a single non-inverting half. A transimpedance amplifier is designed using the half-shared structure to minimize the size per amplifier. The transimpedance amplifier is based on a current integration of a capacitor. The noise analysis of the integration amplifier is a challenging task because it does not reach a steady-state, thus, being a non-stationary circuit. For frequency analysis, a conversion method is discussed to estimate the noise characteristic in the simulation. The array design of 1024 transimpedance amplifiers is fabricated using a standard 0.35 μm process and is tested to confirm the validity of above analysis. The amplifier array exhibits high linearity in transimpedance gain (7.00 mV/pA for high gain and 0.86 mV/pA for low gain), low mismatch of 1.65 mV across the entire 1024 amplifier array, and extremely low noise. The technique will be crucial in enabling the fabrication of larger arrays to enable higher throughput measurement tools for biosensor applications.

Low‐power, high‐speed output buffer with shared‐TIA for ultra‐large IRFPAs

In this Letter, a low-power, high-speed output buffer for ultra-large infrared focal plane arrays (IRFPAs) is proposed. This buffer adopts a shared trans-impedance amplifier structure, which reduces parasitic resistance and capacitance of column-level bus. A 1280 × 1024 array readout integrated circuit with 20 MHz output frequency is designed for cooled infrared detector using this novel structure. The chip has been realised with 0.35 μm 1P4M CMOS process and power consumption of the proposed single output buffer is 3.83 mW. Though the presented circuit has been designed for this design, it shows great potential to be employed in most ultra-large readout integrated circuits.

Design of CMOS Power Amplifier for LTE MTC System Transmitter

An high linearity power amplifier based on TSMC 65nm LP CMOS process was designed, which can meet the application requirements of LTE MTC communication standards in 1.8 8∼1.92GHz band, and the average efficiency was improved. As the core module of the system, the power amplifier employs a two-stage linear amplifier structure, and implemented with the technique of lossy networks and matching compensation, meets the requirements of indicators in wide-band range. According to the post-simulation results, in the working frequency band of 1.88∼1.92GHz, the proposed PA achieves maximum output power of more than 26dBm, power gain is over 20dB.The OP1dB is more than 24dBm,and the power added efficiency (PAE) at OP1dB is over 25%.The simulated S11 is under -10dB and achieved good input matching feature.

Low-noise and high-gain of stimulated Brillouin amplification via orbital angular momentum mode division filtering.

We demonstrate a Brillouin amplifier scheme by using orbital angular momentum mode division filtering, which is able to amplify the weak optical signals with low noise and high gain. The system retains the advantages of a conventional collinear Brillouin amplifier structure, and employs a liquid-crystal spatial light modulator to generate distinguishable degree-of-freedom of beams. As we all know, the noise mainly derives from the unwanted coupling in stimulated Brillouin scattering (SBS) processes, which severely limits the amplifier's performances. The efficient SBS noise-filtering method is discussed, which could improve the output beam quality effectively. The experimental results show the proposed amplifier scheme can overcome this obstacle, providing the magnification (or called signal gain) of 71dB for an input signal of 4.7×10-12 J. In addition, the amplified signal is recognized from the amplifier spontaneous-emission (ASE)-like noise with a signal-to-noise ratio of 6.7dB.

Temporal Auto-Correlation Function Pushed to One Pixel Limit

Quantum transport in a neutral atom guide provides intriguing quantum effects that are important aspects in designing atom mechatronic structures such as quantum interferometer, pump, valve, and amplifier structures. We investigate applicability of spatial reduction in temporal auto-correlation function to reduce computational resources in finding eigen-energy inside the guide. We find that we can reduce the size of the correlation function to an area 65,536 times smaller than the entire simulation space (0.0015%), which corresponds to an area of one pixel. The maximum error of all energies is 8.18% for a ground state and the trend of errors reduces exponentially as the principle quantum number increases. The setting of the investigation involves initial Gaussian wave packet evolving in a 2D harmonic potential and the correlation space is concentric to the center of the initial wave packet.

Humidity and temperature sensor system demonstrator with NFC tag for HySiF applications

Abstract. Hybrid System-in-Foil (HySiF) is one of the emerging branches of flexible electronics in which ultra-thin silicon chips are integrated with flexible sensors in polymeric foils (Elsobky et al., 2018; Alavi et al., 2018). Intensive attention was given to the implementation of flexible environmental sensing platforms for logistics and food packaging (Cartasegna et al., 2011; Liu et al., 2016). The aim of this work is the implementation of a sensor system demonstrator using HySiF components, namely an ultra-thin microcontroller chip in addition to an on-chip temperature and an on-foil humidity sensors. The measurement concept for the relative humidity sensor is measuring the capacitance difference between an off-chip (on the foil substrate) humidity dependent sensor capacitor, and another humidity independent reference capacitor. The electrical readout technique is based on the charge amplifier switched capacitor circuit. It is implemented using a commercially available microcontroller (EM microelectronics EM6819) which has the advantage of being available as single chips to enable post-processing steps such as backthining and chip embedding in a thin polymer package. Sensor and reference capacitors are homogeneously integrated on-foil. 400 and 30 µm thick microcontroller dies (MCU) are used in this application. The charge amplifier result is digitized using an internal 10-bit analog-to-digital converter (ADC). The 10-bit ADC is time multiplexed between the charge amplifier structure and the internal temperature sensor. Linear interpolation is used to fit the digital output of the ADC and calibrate the output of the sensor system. Readings of the humidity level and the temperature are written to an NFC tag (from the company EM microelectronics based on chip EM NF4) using the contact interface. Readings can be accessed using a customized android application on a smartphone.

A fully-integrated 16-channel EEG readout front-end for neural recording applications

In this paper, a power-efficient, low noise analog front-end (AFE) is presented which employs the chopper-stabilized technique. A new instrumentation amplifier structure leads to a high input impedance beyond 10 GΩ at the frequency of 10 Hz. Furthermore, an adaptive DC servo loop (DSL) is proposed which is conditionally activated to minimize the negative impact of this block on the noise performance of the AFE. The integrated input-referred noise of the amplifier is 1.33 µVrms and 1.19 µVrms over the 0.5 Hz–100 Hz frequency range when the DSL is enabled or disabled, respectively. Also, considering different aspects of the AFE, a new comprehensive figure of merit (FOM) is introduced to compare different state-of-the-art biopotential amplifiers. The power consumption and bandwidth of the designed 16-channel AFE are 15.81 µW and 235 Hz, respectively. The circuit is realized in the 180 nm standard complementary metal–oxide–semiconductor technology using a 1 V power supply.

0.18 mW/pole inverter‐based G m ‐C bandpass filter with automatic frequency tuning

A low-power Gm-C filter with the elliptic prototype targeting wireless application of the IEEE 802.15.4 (ZigBee) standard is presented. A modified inverter-based Gm cell is proposed to increase the current efficiency. Due to the tail current source, this Gm cell also shows better common-mode rejection and power supply rejection performance than traditional operational transconductance amplifier (OTA) structure. The filter is implemented in a 65 nm CMOS process. It achieves a figure of merit of 0.01 fJ with a power consumption of 0.18 mW/pole from a 1.2 V supply voltage. It provides stopband attenuation better than 40 dB, and an in-band IIP3 of 9 dBm. An automatic frequency tuning circuit based on sine-wave PLL method is introduced to compensate for the process variations. The centre frequency and bandwidth can be simultaneously tuned to satisfy the specifications. They are also stable over the process variations with only 2.3% deviation.

Effect of the Number of Longitudinal Modes on Spectral Broadening in a High Power Fiber Amplifier

The dependence of the spectral broadening characteristics on the number of longitudinal modes is studied experimentally in a bi-directional pumping fiber amplifier. It is found that the linewidth of the amplifier decreases with reducing the longitudinal mode number of the seed source. In this letter, we present a 68 pm-linewidth kilowatt-level fiber laser using a simple master oscillator power amplifier structure. Meanwhile, we theoretically analyze the spectral broadening characteristics of the seeds with different longitudinal mode numbers. The conclusions are in agreement with the experimental results. This provides a simple and efficient method for obtaining the high power narrow linewidth fiber laser used in spectral beam combining.

A 6–18-GHz GaN Reactively Matched Distributed Power Amplifier Using Simplified Bias Network and Reduced Thermal Coupling

Two-stage reactively matched gain cells are proposed to implement a high-gain multioctave distributed power amplifier (DPA). The proposed reactively matched distributed amplifier (RMDA) structure shows high gain and power in a small die size. Detailed analysis is presented to understand the design criteria for interstage matching of reactively matched cells. A shared dc bias network is proposed to simplify the biasing of each section to reduce the DPA die size. The thermal coupling effect of GaN high-power amplifier is minimized by optimizing the chip layout. The theoretical analysis is verified by the simulation and supported by the measured data. Two RMDAs are fabricated with a commercial 0.25- $\mu \text{m}$ GaN HEMT process. The implemented RMDA with the compact transistor layout has been implemented in a small die size of 10.7 mm2 and shows output powers reaching 40.3–43.9 dBm, power added efficiencies (PAEs) of 16–27%, and small-signal gains of 15.3–23.2 dB. The RMDA with the reduced thermal coupling achieves 40.6–43.4 dBm with a peak PAE of 29% in a slightly larger die size of 13.8 mm2. To the best of our knowledge, this is the first demonstration of a GaN DPA using reactively matched gain cells, showing very high gain and efficiency over multioctave bandwidth in a small die size.

Noise of a JFET Charge Amplifier for Piezoelectric Sensors

A comprehensive noise model of a junction gate field-effect transistor (JFET) charge amplifier is presented for applications with piezoelectric sensors. Based on this previously reported amplifier structure, a noise equivalent circuit is derived and discussed. Universal noise gain expressions for each of the twelve considered noise sources are given. By means of an analytical description of the charge amplifier’s noise behavior, the design and optimization of such preamplifiers for various capacitive microelectromechanical sensor systems will be distinctly simplified. Calculations of the noise floor are compared with measurements with a cantilever-type magnetoelectric sensor and with the performance of a so far commonly utilized basic charge amplifier. With the JFET charge amplifier a noise reduction of approximately 22 dB is achieved in the vicinity of the utilized sensor’s resonance frequency of 7.45 kHz. The reported amplifier is the first which has no negative influence on the total noise level of a resonant magnetoelectric sensor system.

Analysis and Design of a Broadband Frequency Divider Using Modified Active Loads in GaAs HBT

A modified divide-by-2 regenerative frequency divider (RFD) is presented in this paper. The effects of modified active loads on the bandwidth of RFD are demonstrated and analyzed in detail by introducing the equivalent circuit using [Formula: see text] model. Using the transimpedance amplifier structure with resistive shunt–shunt feedback and shunt-peaked inductor as the active loads of the generative frequency divider, the loop bandwidth and the loop gain can be increased at higher frequencies to extend the bandwidth. Based on the theoretical analysis and design methodology, an RFD with improved active loads is designed and fabricated in 1[Formula: see text][Formula: see text]m GaAs heterojunction bipolar transistor technology with a total chip area of 0.83[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]0.75[Formula: see text]mm. The measured phase noise at the divider output is less than [Formula: see text]110[Formula: see text]dBc/Hz with 100[Formula: see text]kHz offset and is [Formula: see text]127.6[Formula: see text]dBc/Hz with 1[Formula: see text]MHz offset. The operation frequency range is from 10 to 26[Formula: see text]GHz. The power consumption of the divider core is 166.44[Formula: see text]mW, and the frequency bandwidth is 16[Formula: see text]GHz at a supply voltage of [Formula: see text]6[Formula: see text]V.

High-Power Narrow-Linewidth Tunable 670.8-nm Master Oscillator Power Amplifier With High Efficiency

A highly efficient 670.8-nm high-power narrow-linewidth wavelength-tunable laser source with master oscillator power amplifier structure is demonstrated, which yielded CW output power of 4.5 W with spectral linewidth of 0.3 pm and mode-hop free tuning range of 52 pm (35 GHz). The total conversion efficiency of 20% was achieved. The developed narrow-linewidth tunable laser source can provide better performance than others ever reported at 670.8 nm for many applications, such as laser isotope separation, Bose–Einstein condensation experiments, and mid-infrared laser generation.

A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.