CMOS Amplifier Research Articles

Voltage lowering and gain control techniques for a single-supply-driven 0.7 V amplifier

A CMOS amplifier architecture is presented with a voltage lowering technique so that it can be driven from a single 0.7 V bias supply. The topology does not need scaled gate voltages (or additional bias circuits) and uses branching of its bias path to reduce power requirement. A three-stage cascaded structure is adopted for high gain with the output common-drain block realizing a gain control mechanism. The technique achieves 6 dB gain regulation (with a control voltage) at the expense of small additional power (1.27 mW). A K-band architecture is simulated with a 90-nm CMOS process to verify the proposed mechanisms. The low-power (7.37 mW) unregulated front-end achieves 27 dB gain with a noise figure range of 2.99–3.06 dB within the 20.5–22.2 GHz bandwidth. Port reflection loss figures ( and ) are analysed to be −8 dB and −11 dB. The circuit has an area requirement of 0.62 mm2 and performs better in terms of power supply requirement and potential packaging cost when compared with simulated results of published millimetre-wave amplifiers.

High frequency CMOS amplifier with improved linearity

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved.

A Feedback Technique to Compensate for AM-PM Distortion in Linear CMOS Class-F Power Amplifier

An amplitude-phase (AM-PM) linearization technique using a direct drain-gate feedback method in a cascode CMOS amplifier is proposed. This technique consists of a series-connected capacitor and an inductor coupling the residue of the RF signal drain. The coupled RF ac signal to gate node of the common gate stage (CG) prevents the CG stage from entering the triode region at a high output power region. In this respect, the parasitic gate-drain capacitance sustains a constant value, achieving an enhancement in linearity. To verify the superior performance of the proposed technique, a CMOS PA was fabricated using a commercial 0.18 μm process. The experimental results show that the implemented PA delivers a PAE of 34.2% at an output power of 26.7 dBm for a 10 MHz 3G LTE signal at Band 5/8 (824-915 MHz), and has an improved spectral performance of over 5 dBc.

Fast Transient Response Low Drop-Out Voltage Regulator

This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-�m CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages att equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.

Graph-Based Symbolic Technique for Improving Sensitivity Analysis in Analog Integrated Circuits

Sensitivity analysis methods have been widely applied to electronic circuit design. However, the majority of them are based on formulations dealing with large matrices. That way, this article introduces the application of a new graph-based symbolic technique (GBST) for improving the symbolic sensitivity analysis of integrated circuits (ICs). In addition, the computed sensitivities are ranked to enhance the design and optimization of analog ICs. The proposed GBST is compared with two traditional approaches, namely: adjoint network and incremental network. We show that the three symbolic sensitivity techniques compute the same sensitivity ranking order, while the proposed one is more suitable for amplifiers with a large number of circuit parameters. Two CMOS amplifiers are used as cases of study to highlight the usefulness of our proposed GBST-based approach for performing sensitivity analysis oriented to optimize analog ICs.

Graphene/Si CMOS hybrid hall integrated circuits.

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Differential and common mode stability analysis of differential mm-wave CMOS amplifiers with capacitive neutralization

In this paper differential mode and common mode stability analysis of differential transformer-coupled CMOS mm-wave amplifiers with capacitive neutralization is investigated. Simulation of a differ...

Differential and common mode stability analysis of differential mm-wave CMOS amplifiers with capacitive neutralization

In this paper differential mode and common mode stability analysis of differential transformer-coupled CMOS mm-wave amplifiers with capacitive neutralization is investigated. Simulation of a differential amplifier implemented with a complete PSP transistor model shows that capacitive neutralization can improve the differential stability. In common mode however, the differential pair becomes potentially unstable over a wider frequency range. A robust common mode resistive stabilization technique, which ensures complete stability of the amplifier, is also discussed and analyzed. The analysis and stabilization techniques were successfully applied to stabilize a common mode unstable integrated F-band 45 nm CMOS amplifier. Measurements confirm the stabilization of the amplifier and a differential gain of 16 dB at 110 GHz is achieved.

TFT‐based, multi‐stage, active pixel sensor for alpha particle detection

A multi-stage thin film transistor (TFT)-based active pixel sensor (APS), capable of successfully detecting small impulses of charge resulting from incident alpha particle strikes, is presented. Detection of alpha particles is important in the field of neutron detection, where fully integrated thin-film-based detectors are an attractive alternative to conventional 3He-based proportional counters owing to their low-cost and large-area scaling capability, combined with the use of readily available materials. A typical TFT process, however, produces only N-type devices with low electron mobilities – making high-gain CMOS amplifier designs unfeasible. The disadvantages of using a TFT-only APS design are mitigated by cascading multiple low-gain TFT amplifiers, which results in a higher overall pixel gain – subsequently allowing for the successful detection and readout of alpha particle strikes. Presented is a new APS fabricated in an indium gallium zinc oxide TFT process is presented, and successful initial alpha response measurements are reported.

Design 2. 4 GHz 130nm CMOS Low Noise Amplifier Design for Wireless Network

A low noise amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage, low power and low noise amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. An amplifier is linear electronic circuits that may used amplify an input signal and provide an output signal that is a magnified replica of the input signal. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense for maintain high gain and as low as possible noise. Popular LNA topologies are the inductive source degeneration common-source low noise amplifier. The common source low noise amplifier is commonly used for narrow-band applications due to its ease of input matching, high gain and low noise. Using this method, overall gain can be increased and the noise figure of the low noise amplifier can be decreased.. This work we presents a design of a low noise CMOS amplifier realized in a standard 130 nm CMOS technology with 1.3V supply voltage and consumes power less than 200uW with 18dB on given frequency range also have good input and output matching.

Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7× compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes.

Differently Paired Current Feedback for Common Mode Stability in High Performance Two Stage CMOS Amplifiers

Differently Paired Current Feedback for Common Mode Stability in High Performance Two Stage CMOS Amplifiers

Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.

FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology

We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

A 210-GHz Amplifier in 40-nm Digital CMOS Technology

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing

<?Pub Dtl=""?> We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channel's differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{n}$</tex></formula> ) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 µV <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$_{rms}$</tex></formula> and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifier's four channels yields an effective NEF of 1.64. The total power consumption is 15.6 µW, or 3.9 µW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex> </formula> . The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers.

Design a Bioamplifier with High CMRR

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

A Fully Differential Chopper Circuit in 130nm CMOS for Noise Minimization in Sensor Applications

For sensor applications, the bandwidth of interest is generally a few hertz. In this bandwidth, offset and 1/f noise are the dominant sources of error. Chopping technique is an efficient approach to decrease the 1/f noise and low-frequency offset of CMOS amplifiers; thus, in this paper, a proposed chopper circuit to tackle these problems is presented. The chopper circuit is designed using complementary CMOS switches that are optimized to achieve symmetric linear resistance in the range of input signal. The proposed circuit has a low ON resistance that only varies within 8% of its value for a rail to rail input. To validate its operation, it is used to build up a fully differential chopper stabilized CMOS amplifier powered at 1V. The resulting circuit achieves a thermal noise floor of 10 nV/√Hz and reduces the input referred noise corner frequency from 1-kHz to300mHz.

Radio‐frequency amplifier with tunable high‐Q RF bandpass filtering for SAW‐less wireless receivers

An inductor-less on-chip radio frequency bandpass filtering (RF-BPF) technique with tunable centre frequency is proposed to replace the bulky and expensive external SAW filter. The centre frequency of the BPF not only tracks the local oscillation (LO) frequency (f LO ), but also can be shifted from f LO to a controllable offset for low-IF applications. The RF-BPF has been embedded into a single-ended-input differential-output radio frequency amplifier (RFA) and implemented in 65nm CMOS. The RFA draws 3.5 mA DC current from a 2.5 V power supply. Measurement results show that the BPF achieves 16 dB attenuation at 150 MHz offset from the 1.5 GHz centre frequency, and 7 MHz tunable range without changing the LO frequency.

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the Ku-band (13.2–15.4GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2V) and an active current source, <−10dB port reflection loss and 3.25–3.41dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between −35 and −10dB and the circuit demonstrates a peak forward gain of 24dB at 14.2GHz. The output buffer improves the amplifier's forward gain by ∼9dB and pushes down the minimum output return loss to −22.5dB while raising the front-end NF by only 0.05dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The Ku-band amplifier including the buffer block consumes 7.69mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.