Amplifier Design Research Articles

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Investigation of Four-Port Characteristic Dependence on Gate Length for MOSFETs in the Breakdown Region

In this article, gate length-dependent RF four-port characteristics of MOSFETs are investigated in the avalanche regime by using the double feedback and chain rule methods for the first time. The obvious decline of the imaginary part of source input impedance at high drain voltage for short-channel MOSFETs is investigated through the double feedback instead of only the series feedback for the origin of the inductive source impedance. The dominant terms causing the reduction of inductive source impedance due to parallel feedback are determined by this chain rule method. When compared with the conventional analysis due to short-channel effects on the direct-current (DC) characteristics of threshold voltage and substrate current, short-channel MOSFETs resulting in the aspect of RF characteristics are further analyzed by using different gate length MOSFETs. Besides, as gate length reduces, drain-to-source transmission raises significantly in the avalanche regime due to the RF avalanche network according to this analysis. This mechanism results in lower isolation at the breakdown for the shorter gate length MOSFETs. Good agreement of the four-port scattering parameter (S-parameter) between simulation and measurement is obtained for the MOSFETs operating in the both breakdown and saturation regions. The methods can be utilized for other advanced technology nodes and are helpful for the design of RF CMOS amplifiers in the impact ionization region.

A Broadband PA Design Based on Bayesian Optimization Augmented by Dynamic Feasible Region Shrinkage

In this letter, a new Bayesian optimization (BO) method with dynamic feasible region shrinkage (DFRS) technique for power amplifier (PA) design is proposed. As a powerful optimization tool, it provides a more effective way to optimize the performance of PA than the embedded commercial optimization tools. It also has a better convergence speed than the existing fixed mode acquisition function. Results show that the new technique provides a great optimization for PA design, not only for circuit optimization but also for electromagnetic (EM) optimization.

Amplification of high repetition-rate, picosecond laser pulses using a zig-zag slab configuration

Laser sources which generate high peak-pulse energy, picosecond pulse duration outputs at high repetition rates are of particular interest for applications including laser ignition and space fragment detection. In this work, we demonstrate the design and operation of a zig-zag slab, solid-state master oscillator power amplifier (MOPA) which yields high energy amplification. The system uses a weakly-doped Nd:YAG slab as the amplifier medium, to amplify laser pulses from a passively Q-switched microchip seed laser. The seed laser beam undergoes four passes of the slab amplifier resulting in an amplified output pulse with hundreds of picoseconds pulse duration. We investigate the relationship between the angle of incidence of the seed laser beam into the amplifier slab and its effect on the slab fill-factor and overall laser field amplification. We also investigate the impact that the temperature of the laser diode array (LDA) which is used to pump the slab amplifier, has on the amplification efficiency of the MOPA. Experimentally, we demonstrate an amplification factor of ∼90 times from the optimized slab amplifier, and a resultant output laser field with a pulse energy of 99.58 mJ, a pulse duration of 491 ps, and a repetition rate of 200 Hz. We believe that this work will pave the way towards the development of novel all-solid-state amplifier designs for the generation of high-energy, high repetition frequency, sub-nanosecond laser outputs.

12.6 dB squeezed light at 1550 nm from a bow-tie cavity for long-term high duty cycle operation.

Squeezed states are an interesting class of quantum states that have numerous applications. This work presents the design, characterization, and operation of a bow-tie optical parametric amplifier (OPA) for squeezed vacuum generation. We report the high duty cycle operation and long-term stability of the system that makes it suitable for post-selection based continuous-variable quantum information protocols, cluster-state quantum computing, quantum metrology, and potentially gravitational wave detectors. Over a 50 hour continuous operation, the measured squeezing levels were greater than 10 dB with a duty cycle of 96.6%. Alternatively, in a different mode of operation, the squeezer can also operate 10 dB below the quantum noise limit over a 12 hour period with no relocks, with an average squeezing of 11.9 dB. We also measured a maximum squeezing level of 12.6 dB at 1550 nm. This represents one of the best reported squeezing results at 1550 nm to date for a bow-tie cavity. We discuss the design aspects of the experiment that contribute to the overall stability, reliability, and longevity of the OPA, along with the automated locking schemes and different modes of operation.

Design of a broadband Doherty power amplifier with a modified load modulation network

This article proposes a modified load modulation network (LMN) to adjust the structure of the traditional Doherty power amplifier (DPA) by changing one λ/4 microstrip line at the output of the main power amplifier into two in the traditional DPA and connecting a terminal open-circuit λ/2 line at the junction point which can reduce the frequency dispersion effect to achieve expanding bandwidth while maintaining saturation efficiency and back-off efficiency. A 2.6–3.6 GHz DPA is designed and fabricated for verification. The measured results show that the saturated output power is 42.5–44 dBm and the saturated efficiency is between 63% and 69% in target band with a gain from 8.5 to 9.5 dB. At 6 dB output power back-off, the drain efficiency is 44%–50%. And the adjacent channel power ratio (ACPR) is better than −32 dBc.

A 280 GHz 30 GHz Bandwidth Cascaded Amplifier Using Flexible Interstage Matching Strategy in 130 nm SiGe Technology

This paper presents a 280 GHz amplifier design strategy for a robust multistage amplifier in a sub-Terahertz (sub-THz) regime in 130 nm SiGe technology. The presented 280 GHz amplifier consists of 14 stages of the cascaded common emitter (CE) amplifier which offers a compact and improved-noise design due to the absence of the area-expensive and lossy baluns at such high frequencies. The interstage-matching network was flexibly constructed with two separate resonant tanks using metal–insulator–metal (MIM) capacitors and microstrip transmission lines (MSTLs) between each stage. The measured amplifier achieved a peak power gain of 10.9 dB at 283 GHz and a 3 dB gain of bandwidth of 30 GHz between 270 and 300 GHz. The peak output power of the amplifier was 0.8 dBm with an output of 1 dB gain compression point (OP1dB) of −3.6 dBm in simulation. The 14-stage amplifier consumes an area of 0.213 mm2, including all the pads. With the proposed interstage matching approach, a well-balanced 280 GHz amplifier has been demonstrated. The proposed design strategy is widely applicable to sub-THz receivers for future wireless communication systems.

Application of harmonic included CPL‐QPHD model of GaN device for broadband PA design

In this work, a harmonic included canonical piecewise linear (CPL) function based quadratic poly-harmonic distortion (QPHD) model is presented. The proposed model employs the framework of the standard QPHD model, making use of the CPL functions for interpolation of the amplitude of the dominant input signal. Compared with the standard QPHD model, the model described in this work is able to predict transistor behavior at different levels of input powers with one single set of model coefficients. The harmonic information has also been added in this model to make it more complete. The model is validated in terms of both DC and RF behavior through simulated data of a 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) over a wide range of load conditions and power levels. In addition, the model is implemented in advanced design system (ADS) with frequency-defined device (FDD), and applied for a broadband power amplifier (PA) design. Chebyshev low-pass topology is used for both input and output matching network design. Finally, a broadband PA is implemented with an average power added efficiency of 66.23%, an average power of 41.09 dBm, and an average gain of 13.09 dB across the operating frequency range from 0.6 to 1.7 GHz. The simulation results of the harmonic included CPL-QPHD model are highly matched with the measurement results of the designed PA, demonstrating the feasibility of applying the proposed model for broadband PA design.

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

Optimum Transistor Sizing of CMOS Differential Amplifier Using Tunicate Swarm Algorithm

In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Power Amplifier Design

Process Induced Variability (PIV) stemming from fabrication tolerance can impact the performance of integrated circuits. This issue is particularly significant at high frequencies, since Monolithic Microwave Integrated Circuits (MMICs) rely on advanced semiconductor technologies exploiting device sizes at the nanoscale in conjunction with complex passive structures, featuring both distributed elements (transmission lines) and lumped components. Black-box (behavioral) models extracted from accurate physical simulations can be profitably exploited to incorporate PIV into circuit-level MMIC analysis. In this paper, these models are applied to the statistical analysis of a single and of a combined MMIC power amplifier designed in GaAs technology for X-band applications. The relative impact of the active device variability towards the passive matching networks one is evaluated, demonstrating the relevance of PIV. The significant spread found, with only two variable parameters, confirms the importance of a PIV-aware PA design approach, with suitable margins and careful network optimization.

Evaluation of admittance domain behavioural model complexity requirements for Power Amplifier design

In the framework of Power Amplifier (PA) design for communications, frequency domain non-linear behavioural models have shown their potential as efficient complementary modelling tools when Field Effect Transistor compact models are not available or sufficiently accurate. The Admittance behavioural model, formulated in the V-I domain, is especially suitable for device size and fundamental frequency scaling. It is important to note that the direct extraction of this model, from the Nonlinear Vector Network Analyser (NVNA) load-pull (LP) measurements, requires some extra processing since it necessitates a Look-up-Table indexed to |V11| rather than |A11|. When using such models in PA design, there is the need for the user to select the necessary model complexity. To address this requirement, in this paper, a systematic analysis methodology, to guide the user, is presented and validated in different PA design scenarios. The methodology was tested using NVNA LP measurements of GaN Heterostructure FETs. A fifth order Admittance model formulation showed good accuracy in the studied PA design scenarios.

High Gain CMOS Transimpedance Amplifier For Near Infrared Spectroscopy Applications

In this paper, design and analysis of High Gain CMOS Transimpedance Amplifier (HGCTIA) is presented which is greatly necessitated for frequency domain functional Near Infrared Spectroscopy (FD-f NIRS). Generally, feedback resistor and drain resistor play a major role in deciding TIA gain and bandwidth. Most of the research work have utilized only feedback resistor and drain resistor. Here, the gain improvement is greatly achieved by replacing the drain resistor by an active inductor which is designed using CMOS transistor. The active inductor loaded based TIA exhibits only 0.01mW power dissipation which is comparatively lesser than previous research works. Also the proposed design achieves maximum value of transimpedance gain 140dB, bandwidth of 10 MHz, where average noise over the bandwidth is 4.6pA/√Hz with 0.68nArms. Input referred noise is 3.38pA/√Hz. These results are obtained by simulating the proposed approach using cadence 45nm technology. The simulated results shows that the proposed HGCTIA is superior in terms of power, gain and bandwidth.

A Simulated Study of 65 nm CMOS 2GHz Front-End Preamplifier Circuit for Optical Fiber Applications

In this research a new design of the transimpedance amplifier (TIA) with the current mirror was employed by the technique (65nm). The TIA consists of a common gate transistor amplifier (CG TIA) and a common source amplifier as an input stage with local active feedback with a second stage of a current mirror and local active feedback to increase gain. In order to verify the performance of the proposed TIA, a circuit simulation was carried out in the LT spice program using coefficients with the technique (65nm CMOS). The simulation results indicate that the interfacial impedance gain is (41 dBΩ) at a bandwidth frequency of (2.0 GHz-3dB) for an input capacitor of (100 fF) and an input referred noise current spectral density of (14 pA/√Hz) and a power consumption value of (0.091 mw) at an applied voltage (1V). The main focus of this research is low consumption of power and voltage compared to another research.

Simulated Annealing Particle Swarm Optimization for a Dual-Input Broadband GaN Doherty Like Load-Modulated Balance Amplifier Design

In this brief, an automatic power amplifier (PA) design system based on simulated annealing particle swarm optimization (SA-PSO) algorithm is proposed to perform multi-objective optimization in designing broadband Doherty like load-modulated balanced amplifier (LMBA). Specifically, by combining the programming environment with commercial electronic design automation (EDA) software, the optimization process can be implemented automatically. Then, complex and rigorous impedance trajectory aligning at different power levels can be easily obtained using the proposed optimization algorithm, demonstrating the automatic PA design system’s superiority over the built-in optimizer in commercial EDA software for designing broadband Doherty like LMBA. A 2.5-3.5 GHz dual-input Doherty like LMBA is simulated and measured, showing a saturated output power of 45.4-48.2 dBm, a saturation drain efficiency of 60.7% - 69.7%, a 6 dB power back-off DE of 59.2% - 65.8%, and a 9 dB power back-off DE of 52.7% - 66.9%.

Resolution Improvement in a High-Power Magnetic Resonance Imaging Gradient Power Amplifier

High-resolution gradient power amplifiers are required to generate high-fidelity gradient fields in magnetic resonance imaging (MRI) systems. Various aspects of gradient power amplifiers have been the subject of research in the past years, however, systematic analysis and design methods for its resolution improvement have not been sufficiently addressed. This article addresses this research gap with comprehensive analysis and design methods for resolution improvement. First, a method for systematic resolution characterization of the MRI gradient power amplifier with gradient coil is proposed. Second, noise modeling with respect to the critical aspects in the system resolution degradation is developed and discussed. Third, the resolution improvement methods of bandwidth optimization, pseudorandom code modulation, and utilizing silicon carbide (SiC) switching power devices are proposed and analyzed, achieving a resolution at the one part in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${10^6}$</tex-math></inline-formula> level. Finally, the resolution improvement methods are experimentally validated in a 1000 V/400 A SiC gradient power amplifier. The experimental results show a 3.6 times reduction in the peak spurious signals and resolution improvement at all current levels and pulse lengths, compared to a conventional insulated gate bipolar transistor GPA. These results prove the validity of the proposed methods for resolution improvement in a high-power MRI gradient power amplifier, enabling future high-power and high-resolution amplifier designs.

W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication

This article presents a pair of W-band phased-array transmitter (TX) and receiver (RX) chipsets in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS process for high data-rate wireless communication. Both the chips integrate four compact front-end channels in 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 distribution, and the distance between the adjacent RF pads is less than 1.8 mm ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.56\lambda $ </tex-math></inline-formula> at 90 GHz) to fit for the tight antenna array and enable array scaling by tiling multiple unit cells. A 6-bit active phase shifter based on the improved phase-inverting variable gain amplifiers is leveraged to achieve high phase-shift precision and bandwidth concurrently. A noise reduction technique using a parallel inductor to resonate with the parasitic capacitors of the cascode transistors is adopted in the low-noise amplifier design. A novel miniature power combiner, which occupies a much more compact area than the Wilkinson power combiner while delivering great RF performance, is proposed and elaborately analyzed. System-level calibration for local oscillator (LO) leakage and dc-offset suppression is enabled by introducing digitally controlled current sources into the up-conversion and down-conversion mixers. On-wafer measurements for the TX chip exhibit a single-channel IF-to-RF conversion gain (CG) of 26 dB, a competitively high output 1-dB compression point (OP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) of 11 dBm. The RX chip achieves an RF-to-IF CG of 19.5 dB with 9-/14-GHz IF/RF 3-dB bandwidth, a noise figure of 7.7 dB, and an input 1-dB compression point of −28 dBm. The phase-shift characteristics are verified by the TX/RX front-end measurements, achieving a 6-bit phase resolution with minimum rms phase/gain error smaller than 0.83°/0.45 dB and a large phase-shift bandwidth higher than 20 GHz. Preliminary wireless transmission test using a low-cost die-on-printed circuit board (PCB) prototype demonstrates wireless data rates of 1.6 and 0.8 gigabits per second (Gb/s) at distances of 0.4 and 1 m with 256-quadratic-amplitude modulation (QAM) and 16-QAM modulated signals, respectively.

An enhanced ultra-wideband single phase hybrid supply envelope tracking modulator for modern wireless communications

This paper presents a Single Phase Hybrid Supply Envelope tracking Modulator (HSEM) for RF-Power Amplifiers (RF-PAs) used in modern wireless communication systems such as 5G and 6G applications. The proposed HSEM consists of an ultra-wideband linear amplifier to track the input signals with several Mega Hertz of bandwidth, a switching amplifier to provide a high-efficiency supply voltage for the main power amplifier, and a new sensing circuit to generate the required voltage for the switching amplifier. The designed HSEM uses a two-stage rail-to-rail linear class-AB amplifier with constant Gm, high gain bandwidth (GBW), high slew rate (SR), and good phase margin (PM). Most conventional modulators use a sensing resistor or a resistor structure that increases the output ripple and the power loss. The proposed structure uses a linear amplifier output stage sensing circuit and a hysteresis low power current comparator without any resistors, external capacitors, filters, or multi-phase modulator structures. Additionally, using a current comparator eliminates the need for an external reference voltage or a current-to-voltage converter. The proposed structure does not need to remove the switching ripple through the linear amplifier, leading to a more relaxed linear amplifier design. A comprehensive analysis and guide on how to optimally select the inductor values, and the mathematical equation for the switching frequency of the hybrid modulator is given. The efficiency of the proposed structure is 84.3 %, and the maximum output power is 27.3dBm. The average output ripple is 4.16 mV in the wide range of the input voltages, and its minimum is 0.4 mV. In addition, the new structure can track a signal with 400 MHz bandwidth with FOM of the HSEM about 18. The proposed modulator is suitable for broadband and emerging telecommunications applications such as 5G and 6G, and as a power supply for RF power amplifiers. The proposed HSEM is evaluated with TSMC 180 nm CMOS technology parameters.

Machine Learning and Rules Induction in Support of Analog Amplifier Design

The aim of the paper is to present a two-step method for facilitating the design of analog amplifiers taking into account the bottom–top approach and utilizing machine learning techniques. The X-chart and a framework describing the specificity of analog circuit design using machine learning are introduced. The possibility of libraries with open machine learning models to support the designer is also discussed. The proposed method is verified for a three-stage amplifier design. In the first step, the stage type is predicted with 89.74% accuracy as the applied learner is a Decision Tree machine learning algorithm. Moreover, two induction rule algorithms are used for predictive logic generation. In the second step, some typical parameters for a given stage are predicted considering four learners: Decision Tree, Random Forest, Gradient Boosted Trees, and Support Vector Machine. The most suitable is found to be Support Vector Machine, which is characterized with the smallest obtained errors.

Simulating the behaviour of travelling wave superconducting parametric amplifiers using a commercial circuit simulator

Kinetic inductance travelling wave parametric amplifiers (KI-TWPAs) have been simulated using Keysight’s Advanced Design System. A lumped element representation of a superconducting transmission line has been developed using nonlinear inductor elements to represent the current dependency of the intrinsic kinetic inductance. This provides a fast, simple and easily modifiable method for analysing the parametric processes that occur in nonlinear kinetic inductance devices, such as parametric oscillators or amplifiers while also allowing the accompanying RF network to be optimised. This methodology is used to model the behaviour of a select number of KI-TWPA designs operating in the 3-wave mixing (3WM) and 4-wave mixing (4WM) regimes. S-parameters and dispersion properties are extracted from large signal S-parameter simulations, and the gain curve of each amplifier design is generated from harmonic balance simulations. The results are compared to the gain expression from the analytic solutions of the coupled mode equations while making reference to the gain curves of the equivalent KI-TWPAs from literature.