Amorphous Oxide Thin-film Transistors Research Articles

Achieving high performance thin film transistors based on gallium doped indium zinc tin oxide

Abstract In this paper, staggered bottom-gate amorphous oxide thin film transistors with a channel layer of gallium doped indium-zinc-tin oxide (IZTO:Ga) have been fabricated by radio frequency magnetron sputtering at room temperature on SiO2/Si substrate. Under the annealing treatment at 350 °C in air atmosphere, the IZTO:Ga films still kept amorphous and the transmittivity of the IZTO:Ga film was over 80% in the visible range. The IZTO:Ga TFTs showed desired performance with saturation mobility of 36.3 cm2V−1s−1, subthreshold swing value of 0.42 V/decade, current on/off (Ion/Ioff) up to 109 with the off current as low as 4.5 × 10−13 A and exhibited the enhancement mode with a threshold voltage of 1.0 V. Besides, the positive and negative bias stability of the IZTO:Ga TFTs without passivation is also measured in air with the stress time up to 3600 s and the threshold voltage (VTH) showed a shift for +4.6 V and −5.4 V respectively.

Severe hump phenomenon induced by increased charge trapping and suppression of electron capture effect in amorphous In-Ga-Zn-O thin-film transistors under unipolar pulsed drain bias with static positive gate bias stress

This paper demonstrates degradation of amorphous indium gallium zinc oxide thin-film transistors under AC current stress (ACS), which is unipolar AC drain bias applied with positive static gate-bias stress. Under ACS, a severe hump occurs in current-voltage curves; the phenomenon causes a large negative shift similar to degradation caused by positive gate-bias stress (PGS) and a large positive shift by DC-current stress (DCS). In a saturation measurement, the degradation caused by factors in source region had the greatest effect on the hump phenomenon; this result confirms that hump characteristics are caused by charge trapping rather than by defect-state generation by impact ionization. The changes of threshold voltage shifts were extracted at two current levels, then analyzed by comparing with the results of PGS, DCS, and synchronized AC gate and drain bias stress. Positive shift in high-current level was larger after ACS (+3.80 V) than after PGS (+3.48 V) because current-caused Joule-heat thermally energized additional electrons to be trapped in front channel region. Negative shift in low-current level was larger after ACS (−2.42 V) than after DCS (−1.32 V). Under DCS, the amount of positively-charged species decreased because of neutralization of oxygen vacancies. The flow of current supports electron to be captured in ionized oxygen vacancies and the amount of negative shift is saturated at specific value (−1.32 V) under DCS. The characteristic time constant of stretched exponential curve-fitting reveals clear saturation tendency.

Achieving High Mobility and Excellent Stability in Amorphous In–Ga–Zn–Sn–O Thin-Film Transistors

This article reports the fabrication of high-performance amorphous indium gallium zinc tin oxide ( ${a}$ -IGZTO) thin-film transistors (TFTs) with superior bias stability. For comparison, amorphous indium gallium zinc oxide ( ${a}$ -IGZO) TFTs were also investigated to clarify the origin of the superior performance of IGZTO TFTs. It was found that the simultaneous heavy loading of In and Sn into the IGZTO system facilitated an effective mass densification, leading to a reduction in tail states and deep states. The fabricated ${a}$ -IGZTO TFTs exhibited a high electron mobility ( $\boldsymbol {\mu }_{\text {FE}}$ ) of 46.7 cm2/Vs, a subthreshold swing (SS) gate of 0.15 V/decade, and an ${I}_{\text {ON/OFF}}$ ratio $> {1} \times {10}^{{8}}$ . Furthermore, greater gate-bias stress stability was observed for the IGZTO TFTs compared with the IGZO TFTs.

Communication—Wide Bandgap Tin Oxide Thin Film Transistor by Doping Rare Earth Element Europium

–Amorphous europium-doped tin oxide (a-SnEuO) thin film transistors (TFTs) with a wide bandgap of 3.87 eV were prepared by sol-gel method. The results indicate that as Eu content increases, the off-state current of the a-SnEuO TFTs decreases, the threshold voltage (Vth) shifts in the positive direction and the subthreshold swing (S.S.) is also improved. When Eu content is 30 at%, the mobility of a-SnEuO TFTs is 4.5 cm2V−1 s−1, with an S.S. of 0.8 V dec−1. and a switching ratio of 9.5 × 106. Our study indicates Eu-doped SnO2 TFT is expected to be the next generation of display technology.

ALD Al2O3 gate dielectric on the reduction of interface trap density and the enhanced photo-electric performance of IGO TFT.

The amorphous indium gallium oxide thin film transistor was fabricated using a cosputtering method. Two samples with different gate dielectric layers were used as follows: sample A with a SiO2 dielectric layer; and sample B with an Al2O3 dielectric layer. The influence of the gate dielectrics on the electric and photo performance has been investigated. Atomic layer deposition deposited the dense film with low interface trapping density and effectively increased drain current. Therefore, sample B exhibited optimal parameters, with an Ion/Ioff ratio of 7.39 × 107, the subthreshold swing of 0.096 V dec−1, and μFE of 5.36 cm2 V−1 s−1. For ultraviolet (UV) detection, the UV-to-visible rejection ratio of the device was 3 × 105, and the photoresponsivity was 0.38 A W−1 at the VGS of −5 V.

High Performance Transparent a-IGZO Thin Film Transistors With ALD-HfO2 Gate Insulator on Colorless Polyimide Substrate

High performance and transparent amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFT) have been successfully fabricated on the colorless polyimide plastic substrate using a high quality HfO2 dielectric film formed by the low temperature atomic layer deposition process as the gate insulator. Besides, the effects of source/drain material, ITO film and Mo metal, are also studied and compared in this work. With the optimized process condition, the devices with ITO source/drain exhibit a high ION/IOFF current ratio of ~4.25 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> , a lower sub-threshold swing value of 0.087 V/decade, a desirable positive threshold voltage value of 0.1379 V and an acceptable field effect mobility of 19.69 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. while it also shows excellent reliability characteristic and low hysteresis. These results may appear highly promising potentials for the next generation fully transparent flexible display application.

Field-Dependent Mobility Enhancement and Contact Resistance in a-IGZO TFTs

In this article, we performed gated four-probe measurements on amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) to extract their intrinsic mobility and contact resistance as functions of gate voltage and temperature. The abnormal degradation of field-effect mobility was observed in a-IGZO TFTs both at high gate voltage and at high temperature. Results showed that contact resistance played a major role in mobility degradation at high gate bias, whereas band-like transport (phonon scattering) accounts for mobility degeneration at high temperature. We proposed a novel method, which exposed the contact regions to ultraviolet (UV) ozone. The mobility was boosted from 23 to 30 cm2/Vs, nearly 40% increment at high gate bias.

Temperature Dependence Of AOS Thin Film Nano Transistors For Medical Applications.

BackgroundA novel temperature dependent amorphous nano oxide semiconductor (AOS) thin-film transistor (TFT) is reported here for the first time, which is vastly different from conventional behavior. In the literature, the threshold voltage of TFTs decreases with increasing temperature. Here, the threshold voltage increased at higher temperatures, which is different from previously reported results and was repeated on different samples.MethodsElectrical experiments (such as I-V measurements and photoelectron spectrometer experiments) were performed in order to explain such behavior. Double sweeping gate voltage measurements were performed to investigate the mechanism for the temperature dependent behavior.ResultsIt was found that there was a change of trap charge under thermal stress, which was released after the stress.ConclusionNon-Arrhenius behaviors (including a linear behavior) were obtained for the amorphous nano oxide thin-film transistors within 303~425 K, suggesting their potential to be adjusted by measurement processes and be applied as temperature sensors for numerous medical applications.

Bias-dependent subthreshold characteristics and interface states in disordered semiconductor thin-film transistors

The sub-threshold characteristics of a disordered thin-film transistor (TFT) are important, where an interface quality and a demarcation between on and off states of the transistor operation are reflected through the sub-threshold slope (SS). Here, we find that the SS associated with the degree of disorder at the film interface appears to be a function of the gate voltage within the sub-threshold regime. In this respect, we provide an accurate physically-based model to explain this gate bias-dependent sub-threshold slope (SS) for amorphous oxide thin-film transistors whereas the conventional model with the constant SS has a huge discrepancy in comparison with the experimental results. For this, we employ a linear distribution of interfacial states rather than the conventional constant model. The proposed model is applied to the measured sub-threshold current-voltage characteristics for different temperatures lower than 300 K, exhibiting a good agreement with each other.

P‐1.14: The Influence of Bottom gate Dielectric Roughness on the Performance of Double‐Gate a‐IGZO Thin Film Transistors

In this paper,double gate amorphous indium gallium zinc oxide thin film transistors (a‐IGZO TFTs)are investigated in which we use SiO2 deposited by plasma enhanced chemical vapor deposition(PECVD) as bottom‐gate dielectric with different roughness measured by AFM. Our results show that the devices with smaller roughness of bottom‐gate dielectric, which is able to decrease the interface scattering between a‐IGZO surface conducting channel and gate dielectric, can get much larger on state currents and bigger field effect mobilities.Besides,the devices still have good interface properties according to hysteresis curves.

Improving Reliability of High-Performance Ultraviolet Sensor in a-InGaZnO Thin-Film Transistors

High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.

Ultralow Voltage Driving Circuits Based on Coplanar a‐InGaZnO TFTs with Photopatternable Ionic Polymer Gate Dielectric

AbstractCoplanar amorphous indium gallium zinc oxide (a‐InGaZnO) thin film transistors (TFTs) with photopatternable ionic polymer gate dielectrics are fabricated and their inverter/shift register circuits are demonstrated. As a gate dielectric, ionic‐polyurethane acrylate (i‐PUA) can be patterned as small as 20 µm through conventional photolithography to achieve superior electrical properties at low operating voltages by the electric double layer formation, inducing ultrahigh channel capacitance. The fabricated solution‐processed a‐InGaZnO TFT with the i‐PUA gate dielectric shows excellent electrical characteristics such as a field‐effect mobility of 11.6 cm2 V−1 s−1, on–off ratio exceeding 107, and low threshold voltage of 0.3 V. It is also confirmed that the inverter and shift register can be fabricated based on the proposed coplanar a‐InGaZnO TFTs and are successfully functional even at 60 Hz operating frequency with driving voltage levels below 3 V.

Orders-of-magnitude enhancement in conductivity tuning in InGaZnO thin-film transistors via SiNx passivation and dual-gate modulation

The mobility of pristine amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) is insufficient to meet the requirement of the future ultra-high-definition displays. Reported herein is the fabrication of hydrogenated long-channel IGZO TFTs exhibiting a transconductance and an on/off ratio that are orders of magnitude superior to those of the regular devices. The gate bias stability of the treated IGZO TFTs was greatly enhanced, with the threshold voltage shifting by less than 1 V after 1 h stress. Experimentally, the hydrogenation of the active layer was achieved via the deposition of a SiNx/SiOx bilayer on top of the IGZO via plasma-enhanced chemical vapor deposition followed by post-annealing under optimized conditions. The elemental depth profiles indicated that this enhanced performance originated from the hydrogen doping of the IGZO film. Furthermore, a dual-gate structure was fabricated to alleviate the deterioration of the subthreshold properties induced by the excess hydrogen doping.

UV-Cured Hafnium Oxide-Based Gate Dielectrics for Low-Voltage Organic and Amorphous Oxide Thin-Film Transistors.

In this study, we have fabricated hafnium oxide dielectrics for low-voltage organic and amorphous oxide thin-film transistors (TFTs) via a facile low-temperature solution method and investigated the electrical properties of these dielectrics. Hafnium oxide dielectric films can be easily fabricated by a sol-gel solution method and ultraviolet (UV) curing at room temperature. In addition, the surface energy of hafnium oxide films can be easily modified by using phosphonic-acid-based self-assembled monolayers. This modification makes these films compatible with organic semiconductors fabrication methods. These novel dielectrics exhibit excellent insulating properties (leakage current densities of <10-6 A/cm² at 2 V), high capacitances (up to 690 nF/cm²), and smooth surfaces (root-mean-square roughness <0.5 nm). Consequently, hafnium oxide-based dielectrics can be integrated into both pentacene-based and indium oxide-based TFTs, functioning at relatively low voltages (<±3 V) to achieve good performance (hole mobility: 0.31 cm²/V · s, electron mobility: 1.54 cm²/V · s, and on/off current ratios: >105).

Inactivation of low-temperature-induced numerous defects at the electrode/channel interfaces using ultrathin Al2O3 layers

The high demand for flexible and stretchable electronics has resulted in new bottlenecks on the process design of amorphous oxide thin-film transistors (TFTs) fabricated at ≥300 °C that involves low-temperature processes to accommodate for the use of polymer substrates. Unlike previous studies aiming to achieve better channel properties, our study focuses on the low-temperature effects of electrical contacts at the source/drain electrodes and oxide channel junction. The decrease in the process temperature causes unfavorable evident changes from an almost ohmic (350 °C) to Schottky (200 °C) junction and shows coincident trends with the degradation of TFT performances. Thus, we here propose a creative process design using ultrathin Al2O3 interlayers between the electrode and channel, where they inactivate the role of numerous surface defects existing on the a-IZO channels deposited at low temperatures. The a-IZO TFT with 13 Å Al2O3 optimally exhibits a field effect mobility of 17.3 cm2/Vs in the 200 °C low-temperature annealing process, comparable to that of a-IZO TFT annealed at 350 °C. Similarly, the ultrathin Al2O3 interlayers led to the reduced specific contact resistance and ohmic junction behavior. From capacitance–voltage analyses, we elucidated that they were attributed to the significantly reduced trapping events of the charges by passivating the interface defects.

Implementation of Self-Aligned Top-Gate Amorphous Zinc Tin Oxide Thin-Film Transistors

Self-aligned top-gate (SATG) amorphous zinc tin oxide thin-film transistors (a-ZTO TFTs) are fabricated for the first time. Ar plasma treatment forms the self-aligned source/drain (S/D) region and reduces the sheet resistance of the a-ZTO S/D region from a very high value over the measurable limit to around 2.5 $\text{k}\Omega $ /□. The annealing temperature of the a-ZTO film has a strong impact on the electrical performances of the fabricated TFTs. The N2O plasma treatment prior to gate insulator deposition remarkably enhances the TFT performances. The fabricated a-ZTO TFTs present a field-effect mobility of 12.1 ± 0.27 cm $^{\textbf {2}}/\textsf {V}\cdot \textsf {s}$ , a subthreshold swing of 0.3 ± 0.03 V/decade, and good electrical stress stability under both positive and negative biases. A low-cost SATG a-ZTO TFT technology is thus well demonstrated.

P‐6: Development of 1HZ 17.3‐inch Oxide UD HADS Display

Because of the unique property of the low leakage current of amorphous indium gallium zinc oxide (a‐IGZO) thin film transistors (TFTs), the panel can be driven in low frame rate to achieve low power consumption. We have demonstrated low frame rate driving of a prototype of 17.3 inch UD LCD with aIGZO backplane technology. And the panel shows good picture quality even in very low frame rate driving (1Hz) condition. In addition, the key technologies of 1Hz operation have been studied in this work.

Quantitative analysis of annealing-induced instabilities of photo-leakage current and negative-bias-illumination-stress in a-InGaZnO thin-film transistors.

This study examines the effect of the annealing temperature on the initial electrical characteristics and photo-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). The extracted electrical parameters from transfer curves suggest that a low-temperature treatment maintains a high density of defects in the IGZO bulk, whereas high-temperature annealing causes a quality degradation of the adjacent interfaces. Light of short wavelengths below 460 nm induces defect generation in the forward measurement and the leakage current increases in the reverse measurement, especially for the low-temperature-annealed device. The hysteresis after negative-bias-illumination-stress (NBIS) is quantitatively investigated by using the double-scan mode and a positive gate pulse. Despite the abnormal transfer properties in the low-temperature-treated device, the excited holes are identically trapped at the front interface irrespective of treatment temperature. NBIS-induced critical instability occurs in the high-temperature-annealed TFT.

The role of the sequence of plasma treatment and high temperature annealing on solution-processed a-IMZO thin film transistor

In this paper, we reported the effects of the order of plasma treatment and high temperature annealing on solution-processed amorphous indium magnesium zinc oxide (a-IMZO, In:Ga:Zn = 3:1:1) thin film transistors (TFTs). Specifically, we utilized two different processes to fabricate TFTs. In one process, the active layers were plasma-treated (PT, 10 W, 10min) before high temperature thermal annealing (TA, 400 °C), and in another process, the active layers were plasma-treated after high temperature annealing. The former achieves lower off-current (5.83 × 10−12 A) and larger on/off current ratio (2.2 × 107), because the oxygen-related ions in the N2O plasma treatment can passivate the surface of the active layer and reduce the residual organic groups. However, introducing of O2+ and O2− ions leads to an increase in interface defects. The latter sample reaches a mobility 1.97 cm2/V·s, as the generated nanopores during high temperature annealing provide path for more atomic oxygen to infiltrate the film during PT and the oxygen vacancies are reduced. However, the on-current drops sharply with plasma treatment power for the increase of oxidation depth. In addition, all the PT samples show small hysteresis and improved stabilities. Our study suggests that moderate plasma treatment can be adopted to improve the a-IMZO TFT device performances.

Simulation of the effect of deep defects created by hydrogen on the performance of amorphous indium gallium zinc oxide thin film transistor (a-IGZO TFT)

Amorphous indium gallium zinc oxide (a-IGZO) are promising for developing thin film transistors (TFTs) because of their large electron mobility, small threshold voltage (Vth), and low temperature fabrication process. In this study, we have investigated the effect of near valance band defects on the output parameters of a-IGZO TFTs by using two-dimensional TCAD numerical simulation. It was found that donor defects near the valance band have no effect. The degradation of the mobility also causes degradation in the TFT performance. Acceptor defects states near valance band is the reason of positive Vth shift. It is therefore concluded that near valance band defects are not donor defects but acceptor defects with a Gaussian distribution which can also degrade the mobility.