All-digital Delay-locked Loop Research Articles

A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

All-digital transmit beamformer for portable high-frequency ultrasound imaging systems.

To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9ns with a time resolution of 652ps and a maximum lateral resolution error of 0.04mm at 6.8mm.

Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier

This paper presents the impact of radiation-induced Single-Event Multiple Transients (SEMT) in All Digital Delay-Locked Loop (ADDLL) and its impact on the output of frequency multiplier. The performance of the frequency multiplier such as the phase noise and jitter etc. are degraded due propagation of the SEMT from the ADDLL. This paper: (1) shows the impact of SEMTs in the ADDLL in modern technologies, (2) shows how the frequency multiplier circuit performance can vary depending on the severity of SEMTs effects, and (3) demonstrates proposed edge-combined ADDLL based frequency multiplier performance benefits for more reliable operation.

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC.

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m} \times 234\,\,\mu \text{m}$ </tex-math></inline-formula> . The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.

Multi-phases all-digital DLL with multi-input and wide-range delay line

ABSTRACT This paper describes a multi-phase all-digital delay-locked loop with multi-input delay line to achieve a wide range operation. The proposed DLL can generate four phases and the range of operating frequency from 3 MHz to 600 MHz. To save the silicon area, a new structure of delay line proposes to achieve wide range operation. The proposed delay line is implemented with one multi-input cyclic delay cell and four 2-input delay cells. The chip area of proposed DLL is 0.134 mm2. The measured peak-to-peak and root-mean-square are 10.76ps and 1.53ps respectively at 600 MHz while consuming 25 mW under a 1.8 V. The measured results show that the output four phases of DNL and INL are between ±0.013 LSB and 0.015 LSB~-0.011 LSB at 600 MHz, respectively. The proposed circuit has a wider input frequency range and better FOM compared with previous studies. The proposed achieve the lower operation frequency at 3 MHz and smaller phase error at 600 MHz.

PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm2.

High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems

In this article, we present a high delay resolution and all-digital transmit-beamforming circuit for use in high-frequency and wearable ultrasound imaging systems. The proposed transmit beamformer comprises an all-digital delay-locked loop (ADDLL), a cycle-based beamforming delay line (CBDL), and a pulse controller. ADDLL can provide specific digital control code for the CBDL to generate stable and suitable delays to excite array transducer elements without variations in process, voltage, and temperature. CBDL not only provides a finer delay resolution for high-frequency ultrasound imaging systems but also requires a few delay cells to maintain the duty cycle of long prorogation signals, thereby significantly reducing hardware costs. The pulse controller can adjust the number and width of output pulses to meet the requirements of different ultrasonic transducers and Doppler ultrasound color imaging. The proposed transmit beamformer uses a 0.18- $\mu \text{m}$ CMOS technology for a 30-MHz high-frequency linear array with 256 elements, and the focusing depth is from 3.5 to 8.1 mm. The measurement results indicate that the proposed transmit-beamforming design can achieve a maximum time delay of 562.6 ns with an average time resolution of 535 ps. The proposed design offers a smaller volume and finer delay resolution, and it is highly suitable for wearable ultrasound imaging systems.

An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications

The timing skew between signals reduces the timing margin of the receiver and limits the data rate of the parallel link. This issue becomes more critical for applications with many IO pins, such as a high bandwidth memory (HBM). The inter-signal skew compensation scheme for many IO pins requires not only de-skew performance but also the minimization of area and power overheads. In this brief, we propose an inter-pin skew compensation scheme using bypass-controlled all digital delay locked loops (ADDLL). The adoption of the proposed bypass control register that operates with a binary search algorithm, such as the successive approximation register (SAR), allows the digital control delay line (DCDL) controller to be embedded in the delay line. This can alleviate the limitation of bandwidth, which is a disadvantage of SAR and occupies smaller area than SAR whereas maintaining the fast lock time. The circuit is fabricated using a 28 nm CMOS technology with a 1 V supply voltage and an area of 0.0009 mm2 for one de-skew module. The measured result shows that inter-signal skew is reduced to less than 3 ps for 2 Gb/s/pin $\times8$ parallel signals.

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL

This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm2. The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

In this paper, a fast-lock low-power all-digital delay-locked-loop (ADDLL)-based clock generator is proposed that generates fractional multiples of a reference frequency. The proposed clock generator comprises an ADDLL with dual-loop architecture and a fractional frequency multiplier. The coarse tune loop and fine tune loop of the proposed ADDLL can achieve a fast locking time and decrease the static phase error. Moreover, the proposed frequency multiplier can synthesize the 28-phase output clocks of the ADDLL to achieve high multiples. The experimental results demonstrated that the output frequency range of the proposed clock generator was between 176 and 224 MHz, with multiplication factors of 11 ×, 11.5 ×, 12 ×, 12.5 ×, 13 ×, 13.5 ×, and 14 × to cover the very high frequency (VHF) frequency band, where every channel had a bandwidth of 8 MHz. Moreover, the output duty cycle was close to 50% because a divider was used to generate the output signal and the lock time was less than 20 clock cycles. The clock generator was fabricated using a 0.18-μm standard CMOS process, with an active area of 0.59 mm2, power dissipation of 6.7 mW at 224 MHz, and phase noise of − 94.33 dBc/Hz with an offset of 1 MHz. Furthermore, at 176 MHz, the root-mean-square jitter was 25.01 ps, which was less than 0.45% of the output period.

Divider‐less SAR‐based ADDLL

A new all-digital delay-locked loop (ADDLL) using successive-approximation register (SAR) control scheme is presented. The proposed circuit architecture can effectively perform the per-bit acquisition within one clock cycle. Therefore, the divider for generating internal SAR clocks can be further removed to achieve fast-locking capability. Meanwhile, the harmonic-locking problem that often occurs in a wide range of operating frequencies is also eliminated. The test chip is designed and verified with CMOS 0.18 μm technology. The measured acquisition cycles for all operating frequencies (100–800 MHz) are constant as 11 when a 10-bit digital-controlled delay line is employed. The rms/peak-to-peak jitters at the highest and lowest frequencies are 0.775/5.73 and 1.08/8.27 ps, respectively. The chip core occupies an active area of 0.015 mm2 and consumes 9.4 mW at 800 MHz.

1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS

A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.

An All-digital Delay-locked Loop using a Lock-in Pre-search Algorithm for High-speed DRAMs

An All-digital Delay-locked Loop using a Lock-in Pre-search Algorithm for High-speed DRAMs

An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications

In a system on a chip (SoC), there are several long global wires that typically limit the maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been proposed to shorten the length of the global wires. However, the TSV delay variation phenomenon created during the manufacturing process may prevent SoC systems from working properly. This TSV delay variation problem affects data transmission between dies. In this paper, we present an all-digital delay-locked loop (ADDLL) architecture to synchronize clock signals between two dies. We implement the proposed ADDLL in TSMC 90-nm CMOS process with standard cells, which can tolerate process, voltage, and temperature (PVT) variations. In addition, the ADDLL architecture can overcome the TSV delay variation problem using only a single TSV channel. The proposed ADDLL can operate in an input frequency range of 195–960 MHz with a maximum phase error of less than 40.6 ps.