Multi-phases all-digital DLL with multi-input and wide-range delay line

Abstract

ABSTRACT This paper describes a multi-phase all-digital delay-locked loop with multi-input delay line to achieve a wide range operation. The proposed DLL can generate four phases and the range of operating frequency from 3 MHz to 600 MHz. To save the silicon area, a new structure of delay line proposes to achieve wide range operation. The proposed delay line is implemented with one multi-input cyclic delay cell and four 2-input delay cells. The chip area of proposed DLL is 0.134 mm2. The measured peak-to-peak and root-mean-square are 10.76ps and 1.53ps respectively at 600 MHz while consuming 25 mW under a 1.8 V. The measured results show that the output four phases of DNL and INL are between ±0.013 LSB and 0.015 LSB~-0.011 LSB at 600 MHz, respectively. The proposed circuit has a wider input frequency range and better FOM compared with previous studies. The proposed achieve the lower operation frequency at 3 MHz and smaller phase error at 600 MHz.