Logic Simulation Algorithm Research Articles

Optimizing Techniques for Parallel Digital Logic Simulation

A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation has become the major bottleneck in the circuit design process. To alleviate this difficulty, it is possible to make use of parallel (or distributed) circuit simulation. In this paper, we make use of a parallel gate-level simulator which we developed and which is based upon Time Warp. Gate-level simulations exhibit two characteristics which can easily result in either instability or severely degraded simulation performance. Because of the low computational granularity of a gate-level simulation and because the computational load varies throughout the course of the simulation, the performance of Time Warp can be either severely degraded or be unstable. Restraining the optimism of Time Warp via a bounded window and utilizing dynamic load balancing are approaches to deal with these difficulties. In this paper, we make use of learning techniques from artificial intelligence (multiagent Q-learning, simulated annealing) to develop a combined bounded window and dynamic load balancing algorithm for parallel digital logic simulation. We evaluated the performance of these algorithms on open source Sparc and Leon designs and on two Viterbi decoder designs. We observed up to 60 percent improvement in simulation time of one of the decoders using this approach.

A refined F-M partitioning algorithm for logic simulation

Circuit partitioning is an efficient way to speed up the parallel simulation and reduce the communication overhead. How to exploit the parallelism inherent in complex and diverse systems is a research hotspot in simulation area. This paper aims to speed-up the simulation of digital and analogue mixed-signal circuits based on parallel and distributed event simulation (PDES) protocols, using the platforms of a network of workstations (NoWs). Most of partitioning algorithms are heuristic in nature because the graph partitioning problem is NP complete. Based on classical F-M heuristic algorithm, we proposed a multilevel partitioning approach TCFM, which can get fast convergence of F-M algorithm by refining the initial partitioning. The simulator was implemented on network of workstations, a performance matrix was proposed, and a benchmark of ISCAS85 was executed to show that it is feasible to obtain the speedup and lower communication overhead.

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

Multiple-level logic simulation algorithm

An algorithm for the simulation of gate-level logic is presented. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analogue simulator. A Boolean equation solver is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops, and to determine whether the network has no, one or multiple solutions. In the latter case, the solver can identify the nodes whose values are undetermined, thus avoiding the need to initialize all nodes in the network to an unknown state 'X'. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstrated by simulations of a number of benchmark circuits.

Parallel logic simulation on a network of workstations using parallel virtual machine

This paper explores parallel logic simulation on a network of workstations using a parallel virtual machine (PVM). A novel parallel implementation of the centralized-time event-driven logic simulation algorithm is carried out such that no global controlling workstation is needed to synchronize the advance of simulation time. Further advantages of our new approach include a random partitioning of the circuit onto available workstations and a pipelined execution of the different phases of the simulation algorithm. To achieve a better load balance, we employ a semioptimistic scheme for gate evaluations (in conjunction with a centralized-time algorithm) such that no rollback is required. The performance of this implementation has been evaluated using the ISCAS benchmark circuits. Speedups improve with the size of the circuit and the activity level in the circuit. Analyses of the communication overhead show that the techniques developed here will yield even higher gains as newer networking technologies like ATM are employed to connect workstations.

Parallel logic simulation with assignable delays on a vector multiprocessor computer

The author presents a gate level high speed VLSI logic simulation algorithm with an assignable delay that uses bitwise logic operations, together with the segmented waveform relaxation method. Although the proposed technique has some similarity to the compiled code method, it does not generate a compiled code and can handle different delay models, a feature that the conventional compiled code method cannot handle. The proposed technique reduces the memory requirements and computation time by using segmented waveform relaxation, as well as the bitwise logic operations. In addition, the proposed algorithm can be easily implemented on a parallel computer and is structured to take full advantage of parallel processing. Implementation of the algorithm on a shared memory multiprocessor computer using eight processors (ALLIANT FX/8) shows a speedup of over 7 for combinational circuits, and can easily handle tens of thousands of gates.

Concurrency preserving partitioning (CPP) for parallel logic simulation

Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.

Parallel event-driven logic simulation algorithms: tutorial and comparative evaluation

Parallel processing offers a viable way to improve the enormous execution time of the simulation of large VLSI designs. Various parallel logic simulation approaches have been proposed in recent years resulting in some ambiguity as to which scheme offers the best parallelism and execution time. To address these issues, the authors provide a detailed comparison of all four major types of event-driven logic simulation algorithms (synchronous, conservative asynchronous with deadlock avoidance, conservative asynchronous with deadlock detection and resolution, and optimistic asynchronous). The comparisons are carried out on an ideal parallel machine capable of extracting all available parallelism in a given algorithm. The simulation execution time, average parallelism and total messages required for a particular simulation algorithm are measured on the ISCAS combinational and sequential benchmark circuits. The use of an ideal parallel machine exposes characteristics of the simulation algorithms independent of the effects caused by particular parallel architectures or implementations. It is shown that a recently developed conservative asynchronous algorithm of the deadlock avoidance type and the optimistic asynchronous algorithm achieve the best parallel execution time results. However, the new conservative algorithm requires much less implementation overhead than the optimistic algorithm.

Bit-parallel multidelay simulation

The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism. Instead, wide bit-fields containing net-values for several different times are used to resolve out-of-order events. Bit-parallel operations are performed to simulate gates at the required times. The MDP technique was originally designed to be implemented in hardware, but the current software version of the algorithm has proven to be competitive with conventional event-driven multidelay simulation. Two versions of the MDP technique are presented in this paper, fixed alignment and variable alignment. The fixed alignment algorithm provides bit-fields that are wide enough to capture any event that could occur during the simulation of an input vector, while the variable alignment algorithm uses a minimum-width bit field which is just wide enough to capture those events that could occur at an individual step in the simulation. A prototype hardware design is discussed briefly.

Parallel and Vector Logic and Fault Simulation Algorithms on the Cray Y-MP Supercomputer

In this paper, we present parallel algorithms for logic and fault simulation, developed for and implemented on the Cray Y-MP supercomputer, a general purpose shared- memory parallel machine with vector processors. The parallel-and-vector version of the event-driven logic simulation algorithm achieves a speedup of 52 on the Cray Y-MP with 8 processors, with a maximum performance of about 2 million events per second. These results are comparable to the performance of hardware simulation engines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on benchmark circuits [1] show that very high evaluation rates (20 to 32×109 evaluations/s.) can be achieved. Speedup factors of 45 to 69 are observed between the scalar and the parallel and vector execution of the fault simulator.

A query‐based parallel logic simulation algorithm

AbstractLOGIQUE (LOGIc simulation with QUEry) is a parallel logic simulation algorithm for parallel machines with a shared memory. In order to make the best use of the parallelism, queries are issued aggressively. The large overhead in the traditional query‐based parallel discrete event simulation (PDES) algorithm is reduced by replacing the query message with a reference to the shared variables. LOGIQUE has been implemented on a multiprocessor and used to simulate logic circuits. The results, which demonstrate the efficiency of LOGIQUE, are presented.

An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation

We explore the suitability of the Chandy-Misra-Bryant (CMB) algorithm for the domain of digital logic simulation. Our evaluation is based on results for six realistic benchmark circuits, one of them being the R6000 microprocessor form MIPS. A quantitative evaluation of the concurrency exhibited by the CMB algorithm shows that an average of 42-196 element activations can be evaluated in parallel if arbitrarily many processors are available. One major factor limiting the parallel performance is the large number of deadlocks that occur. We present a classification of the types of deadlocks and describe them in terms of circuit structure. Using domain-specific knowledge, we propose and evaluate several methods for both reducing the number of deadlock occurences and for reducing the time spent on each occurence. Running on a 16-processor Encore Multimax we observe speedups of 6-9. While these self-relative speedups are larger than a parallel version of the traditional centralized-time event-driven algorithm, they come at the price of large overheads: significantly more complex element evaluations, extra element evaluations, and deadlock resolution time. These overheads overwhelm the advantages of using distributed time and consistently make the parallel performance of the CMB algorithm about three times slower than that of the traditional parallel event-driven algorithm. Our experience leads us to conclude that the distributed-time CMB algorithm does not present a viable alternative to the centralized-time event-driven algorithm in the domain of parallel digital logic simulation.

A hierarchical compiled code event-driven logic simulator

Logic simulation techniques that reduce both preprocessing time and execution time of unit delay logic simulation are described. Compiled code implementation techniques using a threaded code organization are applied to the event-driven logic simulation algorithm. Simulation speed is increased by a factor of tip to 10 by this technique compared to conventional event-driven simulation. The technique is then extended to hierarchical simulation, in which a fan-out procedure and simulation procedure are generated for each unique module. Hierarchical simulation reduces preprocessing time and allows the recompilation of only those modules that are modified. The simulator uses a portable machine model in which an architecture file describes the target machine. The simulator can be quickly ported to new machines by defining the architecture, while still obtaining high performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modelling and simulation of combinational digital circuits using Petri nets

The P-model approach of modeling a combinational digital network using Petri nets is introduced. In this model a given logic circuit its represented by a graph With only two types of nodes, places and transitions. A logic 1 value in any line of the circuit corresponds to the presence of a so-called token, and a logic 0 corresponds to the absence of tokens, in the corresponding place of the P-model. The operation of the circuit is reflected in the execution of the P-model resulting from the firing of transitions. Several minimizing transformations in the P-model domain are discussed, which reduces the number of places and transitions by an order of magnitude. Based on this P-model representation of a logic circuit, a logic simulation algorithm is outlined. The method is faster and also simpler to implement than conventional simulation techniques.

Distributed and Parallel Demand Driven LogicSimulation Algorithms

Based on the demand‐driven approach, distributed and parallel simulation algorithms are proposed. Demand‐driven simulation ties to minimize the number of component evaluations by restricting to only those component computations required for the watched output requests. For a specific output value request, the input line values that are required are requested to the respective component. The process continues until known signal values are needed (system input signal values). We present a distributed demand‐driven algorithm with infinite memory requirement (but still the memory required at each process is no greater than the sequential demand‐driven simulation), and a parallel demand‐driven simulation with finite memory requirement. In our algorithms, each component is assigned a logical process.The algorithms have been implemented on the Sequent Balance 8000 Multi‐processor machine. Several sample circuits were simulated. The algorithms were compared with the distributed discrete‐event simulation. Our distributed algorithm performed many times faster than the discrete‐event simulation for cases when few results were needed. Parallel algorithm performed 2 to 4 times faster than the distributed discrete‐event simulation.

A hardware logic simulation system

Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel distributed-time logic simulation

The Chandy-Misra algorithm offers more parallelism than the standard event-driven algorithm for digital logic simulation. With suitable enhancements, the Chandy-Misra algorithm also offers significantly better parallel performance. The authors present methods to optimize the algorithm using information about the large number of global synchronization points, called deadlocks, that limit performance. They classify deadlocks and describe them in terms of circuit structure. The proposed methods that use domain-specific knowledge to avoid deadlocks and present a way to reduce greatly the time it takes to resolve a deadlock. For one benchmark circuit, the authors eliminated all deadlocks using their techniques and increased the average number of logic elements available for concurrent execution from 45 to 160. Simulation results for a 60-processor machine show that the Chandy-Misra algorithm outperforms the event-driven algorithm by a factor of 2 to 15. >

Fast functional simulation: an incremental approach

In an effort to speed up simulation, a novel algorithm,, called incremental simulation evaluates the circuit components that can be affected directly or indirectly by design changes, utilizing the information generated during the previous simulation to reduce the number of component evaluations to a minimum. The authors describe the design and implementation of the incremental algorithm for logic or functional simulation, which substantially improves the run-time performance over existing simulators by using the incremental property of the hardware design process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>