Parallel logic simulation with assignable delays on a vector multiprocessor computer

Abstract

The author presents a gate level high speed VLSI logic simulation algorithm with an assignable delay that uses bitwise logic operations, together with the segmented waveform relaxation method. Although the proposed technique has some similarity to the compiled code method, it does not generate a compiled code and can handle different delay models, a feature that the conventional compiled code method cannot handle. The proposed technique reduces the memory requirements and computation time by using segmented waveform relaxation, as well as the bitwise logic operations. In addition, the proposed algorithm can be easily implemented on a parallel computer and is structured to take full advantage of parallel processing. Implementation of the algorithm on a shared memory multiprocessor computer using eight processors (ALLIANT FX/8) shows a speedup of over 7 for combinational circuits, and can easily handle tens of thousands of gates.