Parallel and Vector Logic and Fault Simulation Algorithms on the Cray Y-MP Supercomputer

Abstract

In this paper, we present parallel algorithms for logic and fault simulation, developed for and implemented on the Cray Y-MP supercomputer, a general purpose shared- memory parallel machine with vector processors. The parallel-and-vector version of the event-driven logic simulation algorithm achieves a speedup of 52 on the Cray Y-MP with 8 processors, with a maximum performance of about 2 million events per second. These results are comparable to the performance of hardware simulation engines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on benchmark circuits [1] show that very high evaluation rates (20 to 32×109 evaluations/s.) can be achieved. Speedup factors of 45 to 69 are observed between the scalar and the parallel and vector execution of the fault simulator.