Parallel logic and fault simulation algorithms for shared memory vector machines

Abstract

Algorithms for logic and fault simulation, developed and implemented on the Cray Y-MP supercomputer, a general-purpose shared-memory parallel machine with vector processors, are presented. The parallel-and-vector version of the event-driven logic simulation algorithm achieves a speedup of 52 on the Cray Y-MP with eight processors, with a maximum performance of about 2 million events per second. These results are comparable to the performance of hardware simulation engines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on benchmark circuits show that very high evaluation rates (20 to 32*10/sup 9/ evaluations/s.) can be achieved. Speedup factors of 45 to 69 are observed between the scalar and the parallel-and-vector execution of the fault simulator. >