Advanced Lithographic Techniques Research Articles

Combining advanced lithographic techniques and self-assembly of thin films of diblock copolymers to produce templates for nanofabrication

A technique to create templates for nanofabrication using thin films of diblock copolymers is discussed and demonstrated. Advanced lithographic techniques are used to create chemically patterned surfaces that manipulate the wetting behavior of diblock copolymer films and to guide the spatial microphase separation of the block copolymer domains. Guided microphase separation has great potential for application of block copolymer films in nanofabrication because of perpendicular orientation of the domains to the substrate and macroscopic perfection in the ordering of copolymer domains. Lithography allows for registration of the domains with the substrate for creating addressable arrays. Experimental implementation of the technique is demonstrated using extreme ultraviolet interferometric lithography, self-assembled monolayers of octadecyltrichlorosilane as imaging layers, and the self-assembly of films of symmetric poly(styrene-b-methyl methacrylate).

Thermal–mechanical performance of extreme ultraviolet lithographic reticles

Thermal deformation of reticles will likely become an important consideration for all advanced lithography techniques targeting 130 nm features and below. Such effects can contribute to image placement errors and blur. These issues necessitate the need to quantify the reticle distortion, induced by the absorption of illumination power, for candidate substrate and coating materials. To study the impact of various substrate and coating materials on reticle performance, detailed three-dimensional transient thermal and solid mechanical models have been developed and extensively applied to predict total placement errors, residual placement errors, and blur on an extreme ultraviolet lithography (EUVL) reticle during scanning. The thermal model includes a bidirectional scanning heat source representative of the illumination incident on the reticle. The heat loads on the reticle are characteristic of an EUVL engineering test stand with a wafer throughput of twenty 200 mm wafers per hour (assuming 80% die coverage and 68% exposure time). This article includes the results which describe the impact of (1) different substrate materials, (2) various degrees of contact conductance between the reticle and chuck, (3) pattern density and arrangement, and (4) temperature variations across the chuck.

The future of lithography after 193 nm optics

The semiconductor industry growth is driven to a large extent by steady advancements in microlithography. The SIA Lithography Roadmap forecasts the continuing advancements necessary to maintain this steady growth and “work-in-progress” predicts accelerating requirements. According to the newly updated Roadmap, the 130 nm generation is anticipated to be available in the year 2003, however the path to get there is no tobvious. It is still up to the semiconductor industries to make a decision on which advanced lithography technique they will employ. To meet the needs of its members, SEMATECH embarked on a program to explore and narrow the technology options on the Roadmap. With a potential end to traditional optical lithography, the choice among Extreme Ultraviolet (EUV or soft X-ray), ion beam, projection e-beam, proximity X-ray, or alternative reflective technologies is not obvious nor guaranteed for success in the time required. The goal to make a data-driven decision by late 1997 is predicated by the apparent lack of resources needed to pursue multiple technology paths.

Mechanical Modeling of Projection Electron-Beam Lithography Masks

The production of microchips with circuit features in the sub-0.13 µm regime will require an advanced lithography technique such as SCattering with Angular Limitation Projection Electron Lithography (SCALPEL). The mask used in this technique is subject to intrinsic and extrinsic loads during fabrication, mounting, and exposure, giving rise to mechanical distortions which lead to pattern placement errors. In order to develop a low distortion mask, finite element models have been created to identify sources of distortion and quantify the resulting errors. The models are then used as predictive tools to optimize the design of the mask so that distortions do not exceed the error budget. The focus of this study was to investigate the mask membrane distortions induced during the fabrication process and pattern transfer for a preliminary test case of a SCALPEL mask. More specifically, out-of-plane and in-plane distortions were calculated and the sensitivity of this response to variations in mask design parameters was determined.

Heterodimensional Schottky metal–two-dimensional electron gas interfaces

This article presents the results of theoretical and experimental studies of the interface between a two-dimensional electron gas (2DEG) and a Schottky metal. Such an interface is an example of a new class of heterodimensional interfaces which have unusual properties with great potential for practical applications in ultrahigh speed and ultrahigh frequency devices. The unique features of such junctions include a very small effective cross section (equal to the product of the thickness of the 2DEG and the device width) leading to a small capacitance, a large breakdown voltage because of the electric field streamlines spreading in two dimensions near the metal–2DEG interface (and in three dimensions near the metal–1DEG interface) and very large electron mobility (especially at cryogenic temperatures) because of the modulation doping. Our capacitance–voltage (C–V) calculations for a 2D-Schottky junction are in good agreement with our experimental data. We also discuss the properties of other heterodimensional systems, including a one-dimensional electron gas–Schottky metal barrier contact which could be realized using advanced lithographic and etching techniques.

Submicron two-layer metal system of selective tungsten and TiW cap metallization

The processing options available to fabricate multilevel metal interconnects are becoming greatly reduced as circuit dimensions enter the submicron regime. Advanced lithography techniques are required, such as x ray, electron-beam, or monochromatic steppers. The choice of metal materials is small, due to resistivity and interconnect dimension requirements. Sputter deposition equipment has difficulty in depositing the metal into the high aspect ratio vias and new processes with superior stepcoverage are required. Other processing technologies are also experiencing difficulties as dimensions shrink. This paper discusses the utilization of certain advanced processing technologies, namely: stepper lithography, TiW capped AlCu metallization, chemical vapor deposition (CVD) tungsten, plasma deposited oxide (tetraethylorthosilicate source), and etchback planarization to successfully fabricate a submicron two-layer metal structure. The test vehicle had via chains increasing in length from 10–8000 vias with dimensions from 0.75–1.5 μm. Serpentine metal patterns ranged from 0.001–1.1 m in length with pitch of 1.75–3.0 μm. Fabrication issues and potential solutions, as well as electrical data obtained from the test vehicle are presented. The electrical data includes metal serpentine yield and via chain data, comparing: (1) warm deposited AlCu, (2) hot deposited AlCu, and (3) CVD tungsten filled vias.

Theory of coupling of electronic systems: Experimental structures using advanced lithographic techniques

This paper focuses on the physics of disorder-induced localization and the important role of advanced material microfabrication technology for realizing novel microstructures as physical models. Present and future microfabrication capabilities for tailoring materials in the submicron and ultrasubmicron range offer the opportunity to fabricate controllable physical models, approaching atomic scale, for the fundamental study of coupling of electronic systems and the effect of dimensionality on transport properties. These physical models will require the ingenious exploitation of advanced lithographic/patterning techniques for controlling lateral dimensions, particularly if this is combined with advanced vapor or molecular beam deposition technique for controlling vertical dimensions. The type of studies discussed here have great significance in understanding and designing highly-dense very large-scale/ultra large-scale integrated (VLSI/ULSI) circuits and interconnecting-lines-dominated neural network IC systems, as well as in the studies of the scaling theories of localization. It is expected that these studies will lead to the design of novel device concepts.

X-ray lithography for VLSI

In order for any lithography to become the preferred technique for the production of very large scale integrated circuit (VLSI) devices, the technique will have to 1) achieve the required resolution and registration and 2) become more cost effective in this capacity for large volume production than its competitors. The advent of advanced lithographic techniques for LSI production has been postponed by substantial advances in conventional lithography. However, integrated circuits with feature sizes of 1 µm or smaller seem to have significant performance and price advantages over current devices. Such submicron feature sizes press noncontact optical lithography up against the laws of physics. Meanwhile, advances in X-ray lithography have occurred and continue to occur at a promising rate. This paper discusses our experience with X-ray lithography at Intel. Most of our X-ray experience is with the Intel 1-Mbit bubble memory because of the small minimum feature size (1.2 µm) and the defect and alignment tolerance of this device. However, this discussion will be geared toward general VLSI applications of X-ray lithography.

Radiation Levels Associated with Advanced Lithographic Techniques

Estimates of the radiation absorbed dose in critical device oxide layers due to x‐ray and direct‐write electron beam lithography are developed. Layered structures of photoresist, aluminum, silicon dioxide, and silicon are used for explicit calculations. It is shown that radiation levels in the Megarad range can be expected for both of these advanced lithographic techniques. The consequences of this process‐induced radiation damage are briefly considered.

Automatic testing and analysis of misregistrations found in semiconductor processing

For advantage to be taken of advanced lithographic techniques it is necessary to be able to measure and understand the causes of misregistrations found in semiconductor lithographic processes. A device for making such measurements is described which is simple, versatile, compatible with standard processes, and has sufficient accuracy for expected requirements. Devices made using this technique can be automatically tested using standard equipment. Analysis is carried out using computer programs and a brief account of the various outputs is given. Results are discussed which show how misregistrations between masks in a set have been measured and errors in the lead screw of an optical step-and-repeat camera quantified. Misregistrations due to distortion of silicon slices have so far been found to be very small and masked by other effects.

High Resolution Lithography Systems: A Review of the Current Status

AbstractThis paper discusses the advantages and disadvantages of advanced lithography techniques under investigation for the fabrication of semiconductor integrated circuits. These techniques are replacing conventional ultraviolet (UV) contact/proximity printing. They employ standard UV radiation (λ = 3500 Å—4000 Å), deep UV radiation (λ = 2000 Å—2600 Å), soft x‐rays (λ = 4 Å—40 Å), and electrons. It is assumed that the reader is familiar with the basic principles of the new methods.

VLSI Processing, Radiation, and Hardening

Process-induced radiation damage to silicon dioxide films is expected to be commonplace for VLSI circuit fabrication. This might be expected to be most serious for the production of radiation-hardened VLSI. In this paper, the oxide damage due to ion processing is reviewed and the radiation levels associated with advanced lithographic techniques are estimated. Implications for radiation-hardened VLSI circuits are considered.