Advanced Integrated Circuits Research Articles

Quasi-visualizable detection of deep sub-wavelength defects in patterned wafers by breaking the optical form birefringence

Abstract In integrated circuit (IC) manufacturing, fast, nondestructive, and precise detection of defects in patterned wafers, realized by bright-field microscopy, is one of the critical factors for ensuring the final performance and yields of chips. With the critical dimensions of IC nanostructures continuing to shrink, directly imaging or classifying deep-subwavelength defects by bright-field microscopy is challenging due to the well-known diffraction barrier, the weak scattering effect, and the faint correlation between the scattering cross-section and the defect morphology. Herein, we propose an optical far-field inspection method based on the form-birefringence scattering imaging of the defective nanostructure, which can identify and classify various defects without requiring optical super-resolution. The technique is built upon the principle of breaking the optical form birefringence of the original periodic nanostructures by the defect perturbation under the anisotropic illumination modes, such as the orthogonally polarized plane waves, then combined with the high-order difference of far-field images. We validated the feasibility and effectiveness of the proposed method in detecting deep subwavelength defects through rigid vector imaging modeling and optical detection experiments of various defective nanostructures based on polarization microscopy. On this basis, an intelligent classification algorithm for typical patterned defects based on a dual-channel AlexNet neural network has been proposed, stabilizing the classification accuracy of λ/16-sized defects with highly similar features at more than 90%. The strong classification capability of the two-channel network on typical patterned defects can be attributed to the high-order difference image and its transverse gradient being used as the network's input, which highlights the polarization modulation difference between different patterned defects more significantly than conventional bright-field microscopy results. This work will provide a new but easy-to-operate method for detecting and classifying deep-subwavelength defects in patterned wafers or photomasks, which thus endows current online inspection equipment with more missions in advanced IC manufacturing.

Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

Abstract Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for Near Threshold Computing (NTC) application to conquer a unique module for achieving full swing borrow output.We evaluate power, delay, energy and the product of energy with delay (EDP) metrics with respect to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a total die area of 60.02 μm2, while the average power, delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. The results revealed that our proposed subthreshold hybrid FS circuit with GLBB scheme successfully achieved more than 10.46% average power consumption, 26.58% energy consumption reductions, and 17.98% EDP savings compared to conventional CMOS configuration and other hybrid counterparts. GLBB circuits with FS achieve performance levels that are not affordable in C-CMOS, DTMOS,and GLBB with full adder configurations. Therefore, the FS circuit serves as an efficient divider circuit in terms of detecting objects for image processing applications.

Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies

As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin’s surface roughness and results in a high interfacial state density (D it ), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel D it by 73.31% vs 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV dec−1, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Low Contact Resistance via Quantum Well Structure in Amorphous InMoO Thin Film Transistors

The amorphous oxide semiconductor (AOS) thin film transistor (TFT) shows promise for use in advanced integrated circuits, such as 2T0C dynamic random-access memory, due to its excellent electronic performance and ability to be fabricated at low temperatures. Nevertheless, the high contact resistance between the metal and AOS restricts the applicability of AOS-TFT. This study demonstrates the achievement of a reduced contact resistance in InMoO (IMO) transistors by using a MoOx interlayer during fabrication. Increasing the oxygen concentration alters the band structure of MoOx and creates a graded Mo-MoOx-IMO structure with a pronounced quantum well at the interlayer between the metal and channel. Consequently, the quantum well’s ability to attract electrons and shape the band edge suppresses the Fermi-level pinning effect, ultimately leading to the establishment of an ohmic contact. The optimized MoOx interlayer showed a significant improvement in contact resistance (∼400%) through the adjustment of oxygen content during annealing procedures. This finding suggests that it is an attractive approach to provide excellent source/drain contacts in future ultra-scaled amorphous oxide semiconductor thin-films.

Analysis of warpage and reliability of very thin profile fine pitch ball grid array

With the evolution of advanced integrated circuit (IC) packaging technology, the use of experiments to identify package performance and life expectation will take a significant amount of time and cost to finish the job. To reduce the cost of research and testing, predictive analyses of reliability and performance using simulation tools have become a feasible approach for the IC assembly industry. Therefore, this study utilized Moldex3D molding simulation software to analyze very thin profile fine pitch ball grid array (VFBGA) packages and established a numerical analysis procedure from the molding and curing process, the post-mold cure (PMC) process, to a thermal cycling test (TCT) to predict the amount of package warpage during processing and reliability after TCT.The results showed that the warpage trends of both experiments and simulations during the same temperature ramping process were similar. In the thermal cycling analysis, potential failure locations were found to be at the copper pillars and redistribution layer (RDL), where the maximum Von Mises stress occurred at the lowest temperature (−65 °C). The fatigue life model, Coffin–Manson model, was used to calculate the potential fatigue life at the two locations, resulting in 1689 cycles (copper pillars) and 9706 cycles (RDL L1).

Understanding epitaxial growth of two-dimensional materials and their homostructures.

The exceptional physical properties of two-dimensional (2D) van der Waals (vdW) materials have been extensively researched, driving advances in material synthesis. Epitaxial growth, a prominent synthesis strategy, enables the production of large-area, high-quality 2D films compatible with advanced integrated circuits. Typical 2D single crystals, such as graphene, transition metal dichalcogenides and hexagonal boron nitride, have been epitaxially grown at a wafer scale. A systematic summary is required to offer strategic guidance for the epitaxy of emerging 2D materials. Here we focus on the epitaxy methodologies for 2D vdW materials in two directions: the growth of in-plane single-crystal monolayers and the fabrication of out-of-plane homostructures. We first discuss nucleation control of a single domain and orientation control over multiple domains to achieve large-scale single-crystal monolayers. We analyse the defect levels and measures of crystalline quality of typical 2D vdW materials with various epitaxial growth techniques. We then outline technical routes for the growth of homogeneous multilayers and twisted homostructures. We further summarize the current strategies to guide future efforts in optimizing on-demand fabrication of 2D vdW materials, as well as subsequent device manufacturing for their industrial applications.

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 105 on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS2 and WSe2 NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (>235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.

Miniaturized AlGaN‐Based Deep‐Ultraviolet Light‐Emitting and Detecting Diode with Superior Light‐Responsive Characteristics

AbstractThe progressive downscaling of silicon‐based microelectronic devices delivers compact and advanced integrated circuits for fast data processing and computing. Similarly, the miniaturization of conventional optoelectronics is also an important frontier of technology for emerging lighting, imaging, communication, and sensing. Herein, this study reports a miniature dual‐functional diode (DF‐diode) with both light‐emitting and light‐detecting functionalities. The proposed micro‐scale DF‐diode exhibits a record high responsivity of 300 mA W−1 at 265 nm with an ultrafast response rise time of 3.7 ns in light‐detecting mode. While operating in emitting mode, it demonstrates an extraordinarily high −3 dB optical bandwidth above 585 MHz with an enhanced external quantum efficiency performance. Significantly, the development of micro‐scale DF‐diodes has opened up a new avenue toward the realization of an effective and long‐distance solar‐blind optical communication system in the future.

Adaptive Weighted Error-Correction Method Based on the Error Distribution Characteristics of Multi-Channel Alignment.

As process nodes of advanced integrated circuits continue to decrease below 10 nm, the requirement for overlay accuracy is becoming stricter. The alignment sensor measures the position of the alignment mark relative to the wafer; thus, sub-nanometer alignment position accuracy is vital. The Phase Grating Alignment (PGA) method is widely used due to its high precision and stability. However, the alignment error caused by the mark asymmetry is the key obstacle preventing PGA technology from achieving sub-nanometer alignment accuracy. This error can be corrected using many methods, such as process verification and multi-channel weighted methods based on multi-diffraction, multi-wavelength and multi-polarization state alignment sensors. However, the mark asymmetry is unpredictable, complex and difficult to obtain in advance. In this case, the fixed-weight method cannot effectively reduce the alignment error. Therefore, an adaptive weighted method based on the error distribution characteristic of a multi-channel is proposed. Firstly, the simulation result proves that the error distribution characteristic of the multi-alignment result has a strong correlation with the mark asymmetry. Secondly, a concrete method of constructing weight values based on error distribution is described. We assume that the relationship between the weight value of each channel and the deviations of all channels' results is second-order linear. Finally, without other prior process correction in the simulation experiment, the residual error's Root Mean Square (RMS) of fixed weighted method is 14.0 nm, while the RMS of the adaptive weighted method is 0.01 nm, when dealing with five typical types of mark asymmetry. The adaptive weighted method exhibits a more stable error correction effect under unpredictable and complicated mark asymmetry.

Low-Temperature Deposition of Diamond Films by MPCVD with Graphite Paste Additive

Modern integrated circuits (ICs) take advantage of three-dimensional (3D) nanostructures in devices and interconnects to achieve high-speed and ultra-low-power performance. The choice of electrical insulation materials with excellent dielectric strength, electrical resistivity, strong mechanical strength, and high thermal conductivity becomes critical. Diamond possesses these properties and is recently recognized as a promising dielectric material for the fabrication of advanced ICs, which are sensitive to detrimental high-temperature processes. Therefore, a high-rate low-temperature deposition technique for large-grain, high-quality diamond films of the thickness of a few tens to a few hundred nanometers is desirable. The diamond growth rate by microwave plasma chemical vapor deposition (MPCVD) decreases rapidly with lowering substrate temperature. In addition, the thermal conductivity of non-diamond carbon is much lower than that of diamond. Furthermore, a small-grain diamond film suffers from poor thermal conductivity due to frequent phonon scattering at grain boundaries. This paper reports a novel MPCVD process aiming at high growth rate, large grain size, and high sp3/sp2 ratio for diamond films deposited on silicon. Graphite paste containing nanoscale graphite and oxy-hydrocarbon binder and solvent vaporizes and mixes with gas feeds of hydrogen, methane, and carbon dioxide to form plasma. Rapid diamond growth of diamond seeds at 450 °C by the plasma results in large-grained diamond films on silicon at a high deposition rate of 200 nm/h.

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

SCAPSM: attenuated phase-shift mask structure for EUV lithography.

The attenuated phase-shift mask (Att. PSM) is proven to be a promising resolution enhancement technology (RET) to improve the imaging performance in extreme ultraviolet (EUV) lithography. However, due to the reflective nature of the mask structure, the serious shadowing effect can affect the diffraction near field of the mask intensely and further impact the lithography imaging. With the purpose of improving the contrast of lithography imaging, a novel structure of the Att. PSM, to the best of our knowledge, is proposed in this paper. By introducing an absorbent sidewall along the edge of the mask absorber, the diffraction and shadowing effects can be mitigated. By applying the Kirchhoff approximation of mask diffraction, the ability of the novel structure to improve imaging performance is theoretically analyzed. Additionally, these analyses are confirmed by rigorous lithography simulations. The simulation results demonstrate that the proposed mask structure can improve the imaging contrast of EUV lithography, which has potential usage in advanced integrated circuit (IC) manufacturing.

Study of oscillation characteristics for quartz crystal oscillators based on equivalent multi‐physics model

AbstractIn recent years, high‐performance quartz‐crystal oscillators (XOs) for integrated circuits have been receiving considerable attention due to their featuring low voltage and high‐frequency stability. However, recent studies tend to focus solely on the impact of temperature as a single factor on crystal oscillator circuits, overlooking the circuit structure of the crystal oscillator itself. In this paper, a novel four‐parameter crystal model of XOs is detailed demonstrated, and analyzed to interpret typical XO oscillation characteristics at room temperature. The relationship between the RLC circuit and the oscillation was investigated. Meanwhile, the study delves into the various factors that influence oscillation behavior, paving the way for a comprehensive understanding of XOs' performance characteristics. temperature sweep simulations were induced to verify the theory and found that the parameter drift and thermal perturbation are close to the theory we proposed, which can be applied in temperature‐compatible XOs. The significance of this study lies not only in its contribution to the design and implementation of compact footprint XOs in the oscillator circuit platform but also in its provision of experimental evidence for fabricating wide temperature range compensated XO devices. The results show that the capacitance in the equivalent model of a crystal oscillator plays a dominant role in shaping the output waveform and exhibits relatively good temperature stability characteristics and serve as a valuable resource for engineers and researchers working on improving the performance and reliability of XOs, ultimately enabling the development of more advanced and efficient integrated circuits.

Research on Parallel Reading and Drawing Techniques for Chemical Mechanical Polishing Simulation Data Based on Multi-Thread

In advanced integrated circuit manufacturing, the quality of chemical mechanical polishing (CMP) is a key factor affecting chip performance and yield. Designers need to use CMP simulation tools to locate and analyze the defects in the layout after the CMP process. However, the advancement of process nodes and the increase in data volume presents a great challenge to the speed of graphical display of CMP simulation data. To solve this issue, we propose a solution that uses multi-threading technology to optimize both data reading and drawing. In the process of data reading, we employ OpenMP and memory mapping (Mmap) technology to achieve parallel reading of file segmentation and propose a fast-string conversion algorithm based on the properties of simulation data. In the process of data drawing, we propose an adaptive downsampling method for data graphical display that combines multi-threading and double buffering technology to enable the parallel drawing of layouts. The effectiveness of this method is verified by testing CMP simulation data of various scales. Compared to traditional methods, this approach improves reading efficiency by over 8 times and drawing efficiency by more than 10 times. Furthermore, it enhances the smoothness of interaction with the CMP simulation tool.

Simple and facile synthesis of single-crystal CeO2 abrasives and its highly efficient removal mechanism on SiO2 film

CeO2 nanoparticles are one of the key abrasives for chemical mechanical polishing (CMP) in advanced integrated circuits. However, synthesizing highly chemically reactive CeO2 often involves ion doping, high-temperature calcination or reduction, which increase cleaning challenges and risk scratching wafers. We developed a simple and facile method for synthesizing single-crystal CeO2. It exhibits superior polishing performance compared to commercial CeO2, with the material removal rate (MRR) increasing to 4141.45 from 3649.99 Å/min and the surface roughness (Sa) decreasing to 0.533 from 0.647 nm. The CeO2 abrasives were characterized by X-ray Diffraction (XRD), advanced microscopy techniques (SEM, TEM), X-ray Photoelectron Spectroscopy (XPS), and Hydrogen Temperature-Programmed Reduction (H2-TPR). It revealed that the synthesized CeO2 has a particle size of approximately 60 nm and its surface was covered with a uniform amorphous layer of ∼ 1 nm. XPS and H2-TPR revealed its high Ce3+ concentration and enhanced oxygen exchange capability. The polishing mechanism was investigated by XPS and High-Resolution TEM (HR-TEM). Under pressure, the CeO2 established Ce-O-Si bonds with the SiO2 surface. Ce3+ provided electrons to the antibonding orbitals of Si-O bonds, effectively breaking stable Si-O bonds and removed SiO2 film in the form of lump SiO2 through mechanical action.

New structure transistors for advanced technology node CMOS ICs.

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g.in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Development of a High‐Frequency Ophthalmic Real‐Time Ultrasound Imaging System Based on a 20 MHz Annular‐Array Transducer

Objective. Ophthalmic ultrasound imaging is a widely used diagnostic method for examining ophthalmic diseases in the clinic. A single‐element transducer is adopted in the traditional ophthalmic ultrasound imaging systems. Although full depth focusing can be achieved using a linear‐array transducer, it is unsuitable for ophthalmic imaging due to its inability to be tightly coupled to the eyeball and its higher cost. Annular‐array‐based systems provide an alternative, striking a balance between image quality and cost. Methods. Here, we present a newly developed high‐frequency ophthalmic real‐time ultrasound imaging system based on an annular‐array transducer. This system uses a custom‐made five‐element, 20 MHz annular‐array transducer encapsulated in a stainless steel housing and mounted in a commercially available handheld mechanical probe designed specifically for clinical ophthalmic imaging. The system uses a printed circuit board scheme and FPGA as the core to complete the hardware system design and realize the ultrasonic echo signal processing and system timing management. Full depth dynamic focusing of each scanning beam was achieved by designing the transmit and receive beamforming. Combined with advanced integrated circuits, the miniaturization and low cost of the overall system are realized. Results. Extensive tests, including hardware, wire phantom, and tissue mimicking phantom measurements, were conducted to demonstrate good performance of the system. The results showed that the designed system can effectively improve the imaging resolution and enhance the depth of field of the image, particularly reducing the blind area of the near‐field. Conclusion. The high‐frequency ophthalmic real‐time ultrasound imaging system based on an annular‐array transducer meets the needs of clinical diagnosis and has a good clinical application prospect.

An aluminum-based hybrid film photoresist for advanced lithography by molecular layer deposition

In the realm of advanced integrated circuits, the demand for novel resist materials becomes paramount as we progress toward smaller process nodes. Inorganic photoresists have received widespread attention due to...

Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights

In the evolution of integrated circuit technology, chip size and performance enhancement stand as paramount and challenging domains of progress. Yet, a dearth of foundational simulations and comparisons for introductory purposes exists. Consequently, this study delves into an introduction of distinct advanced integrated circuit (IC) technologies: CMOS, FinFET, and CNTFET, dissecting their merits and limitations. Subsequently, a preliminary simulation is executed to authenticate specific characteristics inherent to these IC technologies. Discoveries indicate that as IC transistors scale down, there are marked improvements in transistor performance, encompassing aspects such as switching speed, noise immunity, power efficiency, and heat dissipation. Further, a simulation grounded on a NAND gate substantiates certain traits in CMOS and FinFET, specifically switching speed, propagation delay, and noise margin. The results illustrate a superior performance of FinFET over CMOS. Additionally, as CMOS technology scales, its efficacy enhances. Nonetheless, the present research and simulations hold potential uncertainties and constraints, paving avenues for more refined investigations in the future.

Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.