Advanced eXtensible Interface Research Articles

A Review on Design and Verification of Programmable UART with AXI

A Review on Design and Verification of Programmable UART with AXI

Review on Design and Verification of an Advanced Extensible Interface - 4 Slave Devices

An essential part of a system on a chip (SoC) is not just the components or blocks that it contains, but also how these components and blocks are connected to one another. Advanced Microcontroller Bus Architecture (AMBA) is a system that enables the individual blocks to interact with one another. These protocols have established the de facto standard for 32-bit embedded processors because they are widely documented and may be used without the payment of royalties. High-performance and high-frequency system designs may be designed with the aid of the AMBA AXI 4 protocol. It's ideal for systems that need both large bandwidth and low latency since it enables high-frequency operation without the use of complicated bridges. In addition to being compatible with older versions of the AHB and APB interfaces, it also allows for a wide range of possible configurations for the network's interconnects. Without the need for a bridge, many peripherals may be connected into AMBA-based CPUs via the use of this slave interface. By constructing a wrapper over the AXI4 slave interface, the newly created slave interface may also be used to link non-AMBA-based CPUs to a variety of peripherals. These peripherals include SPI, I2C, and UART, amongst others

High Secure Data Transactions in AXI System Bus using Firewall Protection

Abstract: An open-standard, on the chip interconnection protocol called the Advance Microcontroller Bus Architecture (AMBA) is used to link and manage functional blocks in systems on chip (SoC) architectures. An interface definition called Advanced eXtensible Interface (AXI) specifies the IP block interface rather than the connection itself. The point-to-point connections between a supervisor as well as subordinate are defined by the AXI protocol in terms of their signals and time. The existing AXI protocol only has the response mechanism for the slave error and the valid transactions. In this work the high secure data transactions in AXI system bus is introduced using the firewall protection where a certain range of address are protected to access from other master peripherials

Design and Implementation of Advanced Extensible Interface using Verilog

Abstract: Advanced eXtensible Interface, is an interface protocol defined by ARM as part of the AMBA standard. They comprise of AXI4, AXI4 Lite, AXI4 Stream. The AXI specification describes a point-to-point protocol between two interfaces, a master and a slave. The AXI protocol uses 5 channels, 2 for read transactions and 3 for write transactions. One of the key features of AXI4 is its support for burst transactions, which allows for efficient transfer of multiple data items in a single transaction, enhancing data throughput. AXI4-Lite is designed to provide a lightweight and efficient interface for communication between a master device and simpler peripheral devices or memory-mapped registers in a digital system. AXI4-Stream is developed for highthroughput, unidirectional data transfer between different components in a digital system. The design is done in Verilog.

Design and Implementation of an Accelerated DMA Controller based on AXI Bus

Because Direct Memory Access (DMA) hardly consumes processor resources when carrying high-speed data, an accelerated DMA controller based on Advanced eXtensible Interface (AXI) bus protocol is proposed in this paper. The accelerable part of the controller is to replace the CPU for descriptor splitting processing by hardware, which greatly improves the CPU computing power. At the same time, the controller is equipped with eight deeply configured channels, which are used to process different types of tasks. The design supports single transmission of data and linked list transmission type, which can verify the transmitted data and ensure the security of data transmission. In this design, the working frequency of the controller can reach 500M, the power consumption is 1.3mw, and the data throughput rate can reach 40Gbps, which greatly improves the data moving efficiency of the system.

Encryption AXI Transaction Core for Enhanced FPGA Security

The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.

Software and hardware co-design and implementation of intelligent optimization algorithms

In order to improve the operating efficiency of the algorithm, some intelligent optimization algorithms are considered to be implemented on hardware. However, the existing design scheme has the problem of poor versatility. Therefore, this paper proposes a general software–hardware co-design scheme of intelligent optimization algorithms. In the design scheme, the initialization module and fitness module of the algorithm are deployed on the Advanced RISC Machines (ARM) for execution to increase the flexibility of the program. The update module of the algorithm is deployed on the Field Programmable Gate Array (FPGA) for execution to realize the hardware acceleration. The data between ARM and FPGA is transferred through Advanced eXtensible Interface (AXI) bus. In this paper, the PSO, BA, WOA, GWO, CMAES and EO algorithms are implemented with the proposed design scheme. And the six algorithms are tested on thirteen benchmark functions of different types. The experimental results prove the feasibility of the design scheme. In addition, by comparing with software and other implementation methods in execution time, resource occupancy and convergence, the effectiveness and superiority of the proposed scheme are proved.

Image Acquisition and Processing System based on ZYNQ

With the advancement of manufacturing processes, imaging sensors have become more and more sophisticated, the amount of image data generated is increasing, and application scenarios and functional algorithms have become more and more complex. The traditional serial processing method can no longer meet the real-time requirements of image processing. The use of hardware to accelerate image algorithms has become a basic trend in image acquisition and processing systems. Xilinx’s Zynq7000 series chip integrates a dual-core A9 series ARM processor (PS) and an A7 series FPGA (PL). The industry standard AXI interface (advanced extensible interface) is used for information between ARM and FPGA. Interactive. This paper designs an image acquisition and processing system based on Zynq, which collects images through OV5640, uses Zynq as the main control chip to analyze and process the image data, and uses RGB LCD for image display. This article develops the OV5640 video capture IP, LCD driver IP, and image edge detection IP, and calls these key IPs in the ZYNQ system to establish an image capture and processing system that integrates image data collection, transmission, storage, image display, and edge extraction. The overall effect of the system is good, and it can effectively detect the edge information of the target. At the same time, the image collection and display can reach the design target of 60 frames per second, which has strong applicability.

Analysis of the impact on soft error in AXI CDMA based on Xilinx Zynq-7000 FPGA

The paper discusses the impact of single-event effects (SEEs) induced by radiation in an advanced extensible interface (AXI) central direct memory access (CDMA) core based on 28 nm Xilinx ZYNQ-7000 FPGA. Soft errors of CDMA have been tested with an 241Am source using data transmitting between the block random-access memory (BRAM) and external memory (DDR3). Test results show that various kinds of failure emerge in CDMA in different work modes, such as polling and interrupting driven modes. The radiation-induced multi-cell upsets, up to 8-bit, have been observed and the SEEs cross-sections have been calculated. All experimental results demonstrate that CDMA is a key component leading to increasing sensitivity of resulting soft errors in the FPGA. The test methods and results can provide a reference for SEEs evaluation and protection of CDMA IP Core.

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

We propose a network-on-chip (NoC)-based whole system design, whose communication architecture is compatible with the advanced microcontroller bus architecture advanced extensible interface 4 (AXI4) protocol and supports high-performance multiple quality-of-service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets’ round-trip transfer in the NoC. The NoC system contains time-division multiplexing (TDM) and virtual channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags, and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and low-latency NoC system. By applying the traffic converter, the packet latency can be improved.

A novel utilization-aware and power-delay-aware intelligent DMA controller for video streaming used in AI applications

PurposeIn real-time entertainment processing applications, processing of the multiple data streams demands high efficient multiple transfers, which leads to the computational overhead for system-on-chip (SoC), which runs the artificial intelligence algorithms. High-performance direct memory access controller (DMAC) is incorporated in SoC to perform the multiple data transfers without the participation of main processors. But achieving the area-efficient and power-aware DMAC suitable for streaming the multiple data remains to be a daunting challenge among the researchers.Design/methodology/approachThe purpose of this paper to provide the DMA operations without intervention of central processing unit (CPU) for bulk video data transmissions.FindingsThe proposed DMAC has been developed based on the hybrid advanced extensible interface (AXI)-PCI bus subsystem to handle the multiple data streams from the video sources. The proposed model consists of bus selector module, user control signal, status register, DMA-supported address and AXI-PCI subsystems to achieve better performance in analysing the video frames.Originality/valueThe extensive experimentation is carried out with Xilinx Zynq SoC architecture using Very High Speed integrated circuit hardware description language (VHDL) programming, and performance metrics such as utilization area and power are calculated and compared with the other existing DMA controllers such as Scatter-DMA, Gather-DMA and Enhanced DMA. Simulation results demonstrate that the proposed DMAC has outperformed other existing DMAC in terms of less area, less delay and power, which makes the proposed model suitable for streaming multiple video streams.

Embedded firewall for on-chip bus transactions

This article presents a novel approach towards System-on-Chip (SoC) security. Although communications security and operating system hardening have been studied, new application opportunities and menaces have appeared with the incorporation of Multiprocessor-System-on-Chip (MPSoC) into the Internet of Things (IoT). Reliable implementation environments have become necessary, so novel security architectures and solutions have been introduced to protect the vulnerable data, which could be used by plenty of these applications.We propose an Advanced eXtensible Interface (AXI) transaction firewall, which, by checking the type of operation, the physical address, and the bandwidth according to a set of rules, rejects untrusted requests between cores. Results have been performed on a Zynq platform, and obtained results show that the proposed AXI-firewall can prevent unauthorized transactions consuming few hardware resources. Besides, the fully combinational nature of the firewall’s AXI to AXI path entails that the firewall does not affect the overall performance of the system.

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).

IOb-Cache: A High-Performance Configurable Open-Source Cache

Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules. Despite the recent advent of open-source hardware, the available open-source caches have low configurability, limited lack of support for single-cycle pipelined memory accesses, and use non-standard hardware interfaces. In this paper, the IObundle cache (IOb-Cache), a high-performance configurable open-source cache is proposed, developed and deployed. The cache has front-end and back-end modules for fast integration with processors and memory controllers. The front-end module supports the native interface, and the back-end module supports the native interface and the standard Advanced eXtensible Interface (AXI). The cache is highly configurable in structure and access policies. The back-end can be configured to read bursts of multiple words per transfer to take advantage of the available memory bandwidth. To the best of our knowledge, IOb-Cache is currently the only configurable cache that supports pipelined Central Processing Unit (CPU) interfaces and AXI memory bus interface. Additionally, it has a write-through buffer and an independent controller for fast, most of the time 1-cycle writing together with 1-cycle reading, while previous works only support 1-cycle reading. This allows the best clocks-per-Instruction (CPI) to be close to one (1.055). IOb-Cache is integrated into IOb System-on-Chip (IOb-SoC) Github repository, which has 29 stars and is already being used in 50 projects (forks).

MNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA

The convolutional neural networks (CNNs) are a computation and memory demanding class of deep neural networks. The field-programmable gate arrays (FPGAs) are often used to accelerate the networks deployed in embedded platforms due to the high computational complexity of CNNs. In most cases, the CNNs are trained with existing deep learning frameworks and then mapped to FPGAs with specialized toolflows. In this paper, we propose a CNN core architecture called mNet2FPGA that places a trained CNN on a SoC FPGA. The processing system (PS) is responsible for convolution and fully connected core configuration according to the list of prescheduled instructions. The programmable logic holds cores of convolution and fully connected layers. The hardware architecture is based on the advanced extensible interface (AXI) stream processing with simultaneous bidirectional transfers between RAM and the CNN core. The core was tested on a cost-optimized Z-7020 FPGA with 16-bit fixed-point VGG networks. The kernel binarization and merging with the batch normalization layer were applied to reduce the number of DSPs in the multi-channel convolutional core. The convolutional core processes eight input feature maps at once and generates eight output channels of the same size and composition at 50 MHz. The core of the fully connected (FC) layer works at 100 MHz with up to 4096 neurons per layer. In a current version of the CNN core, the size of the convolutional kernel is fixed to 3×3. The estimated average performance is 8.6 GOPS for VGG13 and near 8.4 GOPS for VGG16/19 networks.

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) protocol was initially a bus oriented interface designed for on-chip communication. To offer the possibility of utilizing the AXI4 based processors and peripherals in the on-chip network based system, we propose a whole system architecture solution to make the AXI4 protocol compatible with the Network-on-Chip (NoC) based communication interconnect in the many-core architecture. Due to the out-of-order transaction in the NoC interconnect, which conflicts with the ordering requirements specified by the AXI4 protocol, we especially focus on the design of the transaction ordering units, realizing a high-performance and low cost (area) solution to the ordering requirements by the sequence ID (seq_ID) reuse mechanism and a simple but smart seq_ID synchronization process. Besides, the micro-architectures and the functionalities of the transaction ordering units are described and explained in detail for ease of implementation. The experimental results in a C++ based system simulator show that, compared with the state-of-the-art works, our solution can maximally increase the system throughput by 66.0% and decrease the transaction queueing delay in the master-side ordering unit by 91.2%.

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques.

Design and SV Based Verification of AMBA AXI Protocol for SOC Integration

Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA AXI) provided by the ARM supports the high performance and high frequency system design. The System on Chip (SOC) Integration design needs to meet the low latency and high bandwidth challenges. The complex bridges are necessary when high frequency operations are carried out and there is a need for the interface which meets the requirement for the wide range of the applications, all such requirements without the complex bridges are provided by the AMBA AXI. The verification of such a bus protocol required to make the SOC integration most robust one. System Verilog based verification methodology provides the systematic way of verifying such a SOC to make it as a most reliable one. Also, SV based assertion makes the checking all the protocols specification easier at the verification stage. In the present paper, the general design and verification methodologies for the AXI-Bus and Memory interface for SOC integration is proposed. Verilog based memory and AXI design being done using Verilog HDL and design challenges are discussed. The proposed design implementation supports single and burst based data transfers. The AXI protocol provides the dedicated channels for memory read and write operations. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed and implemented. The System Verilog based verification environment is setup and used for the verification IP development. And SV Assertion based verification is being done to thoroughly check the AXI protocol functionality.

Verification of Driver Logic Using AMBA-AXI UVM

Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM). The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.