Advanced Chip Research Articles

Molecular Marker-Assisted Breeding and Seed Production Techniques for Shenyou R3, a New Premium Aromatic Hybrid Japonica Rice

The advancement of hybrid japonica rice is pivotal for securing japonica rice supplies and bolstering food security. To address prevalent issues such as inconsistent yields, subpar rice quality, and inadequate seed production in existing cultivars, Shenyou R3 was developed using advanced high-density rice gene chip technology, which is characterized by the expression of specific genes. This late-season, premium aromatic variety, characterized by a popcorn-like aroma, was bred by the Crop Breeding and Cultivation Research Institute of the Shanghai Academy of Agricultural Sciences. Shenyou R3 incorporates superior genes such as badh2-E7, Pi2, Xa21, Sdt97, and Hd17, among which, badh2-E7 and Hd17 are inherited from the maternal line, while Pi2, Xa21, and Sdt97 are inherited from both the maternal and paternal lines. Shenyou R3 offers high-quality rice that adheres to national premium grade 2 standards, with level 1 resistance to blast disease, and yields surpassing the control variety Huayou 14 by over 5% in 2022 Shanghai trials. The new hybrid japonica rice Shenyou R3 has high yield potential and nitrogen utilization efficiency. This paper elaborates on the molecular marker-assisted selection process, key traits, quality metrics, and yield performance of Shenyou R3, while also outlining essential cultivation practices.

CHIPS and Science Act: A Catalyst for US Semiconductor Industry

Abstract—The CHIPS and Science Act of 2022, a crucial U.S. law, seeks to strengthen the domestic semiconductor sector and global tech dominance by dedicating $280 billion to research, innovation, and production; reduce foreign reliance; and boost national security. The Act spurred over $200 billion in private investments from major firms, aiming to create 44,000 jobs and achieve a 28% global market share in advanced logic chips by 2033. It also enabled partnership with India for its first semiconductor fabrication facility. Despite challenges such as funding diversions, high costs, skilled labor shortages, supply chain dependencies, and geopolitical tensions, the Act aims to maintain U.S. technological competitiveness and preparedness for future economic and security challenges. Keywords—Chips Act, Semiconductor, Manufacturing, Advanced Packaging

Relay Protection Device Reliability Assessment Through Radiation, Fault Injection and Fault Tree Analysis.

Relay protection devices must operate continuously throughout the year without anomalies. With the integration of advanced technology and process chips in secondary equipment, new risks need to be addressed to ensure the reliability of these relay protection devices. One such risk is the impact of α-particles inducing single event effects (SEEs) on the secondary equipment. To date, there has been limited assessment of the effects of α-particles on relay protection devices from a system perspective. This study evaluates the impact of SEE on relay protection devices through a Monte Carlo simulation, which is verified by α-particle radiation, fault injection, and fault tree analysis. It discusses the influence of SEEs with and without hardening measures in place. Additionally, this study examines the soft error probability when the target processor runs both general workloads and specific application workloads. The current research proposes a low-cost and effective reliability assessment method for secondary equipment considering single event effects. The findings provide new insights for the enhancement of future electric power grid systems.

Self-catalyzed growth of sub-25-nm-diameter InAs nanowire arrays on Si patterned substrate

The feature size of advanced Si-based chips is approaching its physical limit, and it is difficult to continue Moore's Law by simply pursuing the technical route of miniaturizing device size to increase the integrated density. III-V nanowire devices represented by InAs material have much higher mobility than Si based devices, but they have not been successfully applied to CMOS nanowire devices and have not shown excellent performance. The reason is that the hole mobility of III-V materials is much lower than their electron mobility. If the nanowire diameter becomes ultrafine, the quantum confinement effect becomes more prominent, the light hole band will reverse above the heavy hole band, and the hole mobility will be greatly increased. Aiming at the integrability of III-V high mobility CMOS devices on Si, how to prepare ultrafine InAs nanowire arrays on Si/SiO2 patterned substrates has been studied in this work. New method in this work has solved the problem that the nanohole will enlarge due to etching side wall of nanohole by HF process before growth. A technology and mechanism of ultrafine InAs nanowire arrays grown by this method was developed, and the smallest diameter of nanowire in array has reached only 25 nm.

Advanced, Real-Time Programmable FPGA-Based Digital Filtering Unit for IR Detection Modules

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained.

Precise modulation of the debonding behaviours of ultra-thin wafers by laser-induced hot stamping effect and thermoelastic stress wave for advanced packaging of chips

Abstract Laser debonding technology has been widely used in advanced chip packaging, such as fan-out integration, 2.5D/3D ICs, and MEMS devices. Typically, laser debonding of bonded pairs (R/R separation) is typically achieved by completely removing the material from the ablation region within the release material layer at high energy densities. However, this R/R separation method often results in a significant amount of release material and carbonized debris remaining on the surface of the device wafer, severely reducing product yields and cleaning efficiency for ultra-thin device wafers. Here, we proposed an interfacial separation strategy based on laser-induced hot stamping effect and thermoelastic stress wave, which enables stress-free separation of wafer bonding pairs at the interface of the release layer and the adhesive layer (R/A separation). By comprehensively analyzing the micro-morphology and material composition of the release material, we elucidated the laser debonding behavior of bonded pairs under different separation modes. Additionally, we calculated the ablation threshold of the release material in the case of wafer bonding and established the processing window for different separation methods. This work offers a fresh perspective on the development and application of laser debonding technology. The proposed R/A interface separation method is versatile, controllable, and highly reliable, and does not leave release materials and carbonized debris on device wafers, demonstrating strong industrial adaptability, which greatly facilitates the application and development of advanced packaging for ultra-thin chips.

Piezoelectric actuation for integrated photonics

Recent decades have seen significant advancements in integrated photonics, driven by improvements in nanofabrication technology. This field has been developed from integrated semiconductor lasers and low-loss waveguides to optical modulators, enabling the creation of sophisticated optical systems on a chip-scale capable of performing complex functions such as optical sensing, signal processing, and metrology. The tight confinement of optical modes in photonic waveguides further enhances the optical nonlinearity, leading to a variety of nonlinear optical phenomena such as optical frequency combs, second-harmonic generation, and supercontinuum generation. Active tuning of photonic circuits not only is crucial for offsetting variations caused by fabrication in large-scale integration but also serves as a fundamental component in programmable photonic circuits. Piezoelectric actuation in photonic devices offers a low-power, high-speed solution and is essential in the design of future photonic circuits due to its compatibility with materials such as Si and Si3N4, which do not exhibit electro-optic effects. Here, we provide a detailed review of the latest developments in piezoelectric tuning and modulation by examining various piezoelectric materials, actuator designs tailored to specific applications, and the capabilities and limitations of current technologies. In addition, we explore the extensive applications enabled by piezoelectric actuators, including tunable lasers, frequency combs, quantum transducers, and optical isolators. These innovative ways of managing photon propagation and frequency on-chip are expected to be highly sought after in the future advancements of advanced photonic chips for both classical and quantum optical information processing and computing.

Improved Conductivity of Low‐Temperature‐Synthesized Graphene/Cu for CMOS Backend‐of‐Line Interconnect Applications

AbstractThis study proposes a synthesis strategy of high‐quality graphene films on the copper foil at a temperature of 400 °C throughout the graphene growth process without employing high‐temperature annealing. Through continuous CO2 laser pretreatment of the copper foil, the surface smoothness improves, and the removal of copper particles and copper oxide results in fewer defects on the foil. Therefore, the nucleation density of graphene is reduced, leading to a more uniform and continuous graphene film and showing an outstanding quality of graphene with low defects and low resistivity compared with other groups. After laser treatment, the copper foil's resistivity decreases from 1.71 ×10−8 to 1.51 ×10−8 Ω·m. The graphene‐coated on laser‐treated foil experiences an even more substantial decrease in resistivity, from 1.34 ×10−8 to 1.18 ×10−8 Ω·m, marking a significant 11.94% reduction. Excitingly, the groundbreaking technique is taken to the next level by applying it to fine copper interconnects as narrow as 0.4 µm. The experiments confirm the successful cultivation of graphene on these miniature scales, showing the immense potential of the approach. The proposed approach aligns with the demands of contemporary CMOS backend‐of‐line processes, facilitating the seamless incorporation of graphene in advanced chip technologies.

Compute North vs. Compute South: The Uneven Possibilities of Compute-based AI Governance Around the Globe

Governments have begun to view AI compute infrastructures, including advanced AI chips, as a geostrategic resource. This is partly because “compute governance” is believed to be emerging as an important tool for governing AI systems. In this governance model, states that host AI compute capacity within their territorial jurisdictions are likely to be better placed to impose their rules on AI systems than states that do not. In this study, we provide the first attempt at mapping the global geography of public cloud GPU compute, one particularly important category of AI compute infrastructure. Using a census of hyperscale cloud providers’ cloud regions, we observe that the world is divided into “Compute North” countries that host AI compute relevant for AI development (ie. training), “Compute South” countries whose AI compute is more relevant for AI deployment (ie. running inferencing), and “Compute Desert” countries that host no public cloud AI compute at all. We generate potential explanations for the results using expert interviews, discuss the implications to AI governance and technology geopolitics, and consider possible future trajectories.

Effects of die top system and trenches on large thin die mechanical robustness

Abstract Power MOSFET dies in the automotive industry are becoming larger (> 5 x 5 mm) and thinner (< 50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide, in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the frontside strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm polyimide (PI) on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize polyimide coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

AChIP is an efficient and sensitive ChIP-seq technique for economically important plant organs.

Chromatin immunoprecipitation followed by sequencing (ChIP-seq) is crucial for profiling histone modifications and transcription factor binding throughout the genome. However, its application in economically important plant organs (EIPOs) such as seeds, fruits and flowers is challenging due to their sturdy cell walls and complex constituents. Here we present advanced ChIP (aChIP), an optimized method that efficiently isolates chromatin from plant tissues while simultaneously removing cell walls and cellular constituents. aChIP precisely profiles histone modifications in all 14 tested EIPOs and identifies transcription factor and chromatin-modifying enzyme binding sites. In addition, aChIP enhances ChIP efficiency, revealing numerous novel modified sites compared with previous methods in vegetative tissues. aChIP reveals the histone modification landscape for rapeseed dry seeds, highlighting the intricate roles of chromatin dynamics during seed dormancy and germination. Altogether, aChIP is a powerful, efficient and sensitive approach for comprehensive chromatin profiling in virtually all plant tissues, especially in EIPOs.

Free-space direct nanoscale 3D printing of metals and alloys enabled by two-photon decomposition and ultrafast optical trapping.

Nanoscale three-dimensional (3D) printing of metals and alloys has faced challenges in speed, miniaturization and deficiency in material properties. Traditional nanomanufacturing relies on lithographic methods with material constraints, limited resolution and slow layer-by-layer processing. This work introduces polymer-free techniques using two-photon decomposition and optical force trapping for free-space direct 3D printing of metals, metal oxides and multimetallic alloys with resolutions beyond optical limits. This method involves the two-photon decomposition of metal atoms from precursors, rapid assembly into nanoclusters via optical forces and ultrafast laser sintering, yielding dense, smooth nanostructures. Enhanced near-field optical forces from laser-induced localized surface plasmon resonance facilitate nanocluster aggregation. Our approach eliminates the need for organic materials, layer-by-layer printing and complex post-processing. Printed Mo nanowires show an excellent mechanical performance, closely resembling the behaviour of single crystals, while Mo-Co-W alloy nanowires outperform Mo nanowires. This innovation promises the customizable 3D nanoprinting of high-quality metals and metal oxides, impacting nanoelectronics, nanorobotics and advanced chip manufacturing.

Astrophotonics-current capabilities and the road ahead [Invited

Astrophotonics represents a cutting-edge approach in observational astronomy. This paper explores the significant advancements and potential applications of astrophotonics, highlighting how photonic technologies stand to revolutionize astronomical instrumentation. Key areas of focus include photonic wavefront sensing and imaging, photonic interferometry and nulling, advanced chip fabrication methods, and the integration of spectroscopy and sensing onto photonic chips. The role of single-mode fibers in reducing modal noise, and the development of photonic integral field units (IFUs) and arrayed waveguide gratings (AWGs) for high resolution, spatially resolved spectroscopy will be examined. As part of the Sydney regional-focus issue, this review aims to detail some of the current technological achievements in this field as well as to discuss the future trajectory of astrophotonics, underscoring its potential to unlock important new astronomical discoveries.

Low breakdown voltage and CMOS compatible avalanche photodiode based on SOI substrate.

In this work, we present a novel, to the best of our knowledge, lateral avalanche photodiode (APD) with low breakdown voltage and high bandwidth which has the potential to serve as a core device in future large-scale advanced optoelectronic hybrid chips. By taking advantage of a silicon-on-insulator (SOI) substrate combined with a separation absorption multiplier (SAM) structure, the demonstrated APDs exhibit a high gain of 148. Furthermore, the minimum breakdown voltage of the measured device is 6.1 V, which represents the lowest breakdown voltage for Si-APD, making it compatible with the existing CMOS technology for low voltage operation. Benefiting from an ultra-thin top silicon and lateral SAM structure, the problem of edge breakdown has been completely solved. Additionally, a set of device arrays with absorption and avalanche regions of different sizes is also manufactured and compared. Our findings indicate that the proposed APD has fascinating application prospects in the CMOS process-based LIDAR chips.

Article: The US CHIPS Act and Its Impacts on the WTO and China

In 2022 the US enacted the Creating Helpful Incentives to Produce Semiconductors (CHIPS) Act, providing USD 52.7 billion in subsidies to enhance the chip manufacturing capacity of the US semiconductor industry, attract American businesses back and encourage foreign investments. The CHIPS Act utilizes subsidies as a countermeasure against foreign subsidies in order to secure US leadership of the global semiconductor industry and advanced technology. This represents a significant policy change for the US semiconductor industry. The Act includes a guardrail clause aimed at restricting the investment in or export of advanced chips to China and this may potentially result in the fragmentation of the global chip value chain and in heightened geopolitical tensions. This paper discusses the objectives, subsidies, guardrail clause and clawback mechanism in the CHIPS Act, and their legality under the WTO. It also explores the impact of the CHIPS Act on the WTO and China. The US CHIPS Act is a politically sensitive issue of economic importance and legal complexity in the US-China relationship. It will also reshape the geopolitics of the global chip value chain. Subsidy poses a challenge for the WTO, and a more effective discipline on both subsidies and export restrictions should be an urgent need in a future WTO reform agenda.

Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging

Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies.

Genotype-by-environment interactions and local adaptation shape selection in the US National Chip Processing Trial

Key messageWe find evidence of selection for local adaptation and extensive genotype-by-environment interaction in the potato National Chip Processing Trial (NCPT).We present a novel method for dissecting the interplay between selection, local adaptation and environmental response in plant breeding schemes. Balancing local adaptation and the desire for widely adapted cultivars is challenging for plant breeders and makes genotype-by-environment interactions (GxE) an important target of selection. Selecting for GxE requires plant breeders to evaluate plants across multiple environments. One way breeders have accomplished this is to test advanced materials across many locations. Public potato breeders test advanced breeding material in the National Chip Processing Trial (NCPT), a public–private partnership where breeders from ten institutions submit advanced chip lines to be evaluated in up to ten locations across the country. These clones are genotyped and phenotyped for important agronomic traits. We used these data to interrogate the NCPT for GxE. Further, because breeders submitting clones to the NCPT select in a relatively small geographic range for the first 3 years of selection, we examined these data for evidence of incidental selection for local adaptation, and the alleles underlying it, using an environmental genome-wide association study (envGWAS). We found genomic regions associated with continuous environmental variables and discrete breeding programs, as well as regions of the genome potentially underlying GxE for yield.

Design of low-cost digital pulse processing unit for gamma spectrometry

Gamma spectrometers are used to quantify and identify radioisotopes in the sample under test. There is a recent interest around the world in implementing low-cost gamma spectrometers. One of the main parts of the modern gamma spectrometer is the digital pulse processing unit (DPP). The implementation of this unit using advanced microcontroller chips has appeared in recent years as an attractive approach. This is due to its advanced performance and low cost. In this paper, we present a design flow to implement a DPP unit using an ARM Cortex-M3-based microcontroller chip. The sodium iodide detector is the targeted detector for this design. Our prototype is approved experimentally to construct spectrums comparable to commercial devices. And it can cope with input count rates up to 45 kC/s.

Efficient fabrication of bioinspired soft, ridged-slippery surfaces with large-range anisotropic wettability for droplet manipulation.

The droplet lossless directional motion control on slippery surfaces holds immense promise for applications in microfluidic chips, hazardous substance detection, chemical dispensing, etc. However, a significant challenge in this domain lies in efficiently developing soft, slippery surfaces with large-range anisotropic wettability and compatibility for curved scenarios. This study addressed this challenge through a quick 3D printing-assisted method to produce soft, ridged-slippery surfaces (SRSSs) as the droplet manipulation platform. The SRSSs demonstrated substantial anisotropic rolling resistances, measuring 116.9 μN in the perpendicular direction and 7.7 μN in the parallel direction, exhibiting a ratio of 15.2. Combining several extents of anisotropic wettability on a soft substrate could realize diverse reagent manipulation functions. Furthermore, these SRSSs showcased high compatibility with various droplet constituents, impressive liquid impact resistance, self-repair capability, and mechanical durability and thermal durability, ensuring exceptional applicability. As proofs of concept, the SRSSs were successfully applied in droplet control and classification for heavy metal ion detection, mechanical arm-based droplet grab and release, and cross-species transport, showcasing their remarkable versatility, compatibility, and practicality in advanced droplet microfluidic chips and water harvesting applications.

Asymmetric contact-induced selective doping of CVD-grown bilayer WS2 and its application in high-performance photodetection with an ultralow dark current.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) are excellent candidates for high-performance optoelectronics due to their high carrier mobility, air stability and strong optical absorption. However, photodetectors made with monolayer TMDs often exhibit a high dark current, and thus, there is a scope for further improvement. Herein, we developed a 2D bilayer tungsten disulfide (WS2) based photodetector (PD) with asymmetric contacts that exhibits an exceptionally low dark current and high specific detectivity. High-quality and large-area monolayer and bilayer WS2 flakes were synthesized using a thermal chemical vapor deposition system. Compared to conventional symmetric contact electrodes, utilizing metal electrodes with higher and lower work functions relative to bilayer WS2 aids in achieving asymmetric lateral doping in the WS2 flakes. This doping asymmetry was confirmed through the photoluminescence spectral profile and Raman mapping analysis. With the asymmetric contacts on bilayer WS2, we find evidence of selective doping of electrons and holes near the Ti and Au contacts, respectively, while the WS2 region away from the contacts remains intrinsic. When compared with the symmetric contact case, the dark current in the WS2 PD with asymmetric (Au, Ti) contact decreases by an order of magnitude under reverse bias with a concomitant increase in the photocurrent, resulting in an improved on/off ratio of ∼105 and overall improved device performance under identical illumination conditions. We explained this improved performance based on the energy band alignment showing a unidirectional charge flow under light illumination. Our results indicate that the planar device structure and compatibility with current nanofabrication technologies can facilitate its integration into advanced chips for futuristic low-power optoelectronic and nanophotonic applications.