Abstract
The feature size of advanced Si-based chips is approaching its physical limit, and it is difficult to continue Moore's Law by simply pursuing the technical route of miniaturizing device size to increase the integrated density. III-V nanowire devices represented by InAs material have much higher mobility than Si based devices, but they have not been successfully applied to CMOS nanowire devices and have not shown excellent performance. The reason is that the hole mobility of III-V materials is much lower than their electron mobility. If the nanowire diameter becomes ultrafine, the quantum confinement effect becomes more prominent, the light hole band will reverse above the heavy hole band, and the hole mobility will be greatly increased. Aiming at the integrability of III-V high mobility CMOS devices on Si, how to prepare ultrafine InAs nanowire arrays on Si/SiO2 patterned substrates has been studied in this work. New method in this work has solved the problem that the nanohole will enlarge due to etching side wall of nanohole by HF process before growth. A technology and mechanism of ultrafine InAs nanowire arrays grown by this method was developed, and the smallest diameter of nanowire in array has reached only 25 nm.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call