Adjacent Devices Research Articles

Role of oxide charges on the voltage and current coupling effects between adjacent devices examined by concentric metal-insulator-semiconductor (MIS) tunnel diodes with ultra-thin oxide

The impacts of positive oxide charges within the silicon oxide (SiO2) layer on the coupling mechanism in metal-insulator-semiconductor (MIS)-coupled devices were studied. By employing the post-metallization annealing (PMA) process, the condition of coupled devices with fewer oxide charges was established. In terms of coupled voltage, the presence of oxide charges facilitated the transmission of gate voltage-induced quasi-Fermi level splitting to neighboring devices, resulting in the induction of coupled voltage. Conversely, with few oxide charges, no coupled voltage was observed at the neighboring device. Additionally, positive oxide charges induced an inversion channel at the silicon surface, fostering the sharing of minority carriers in the conducting channel between adjacent devices. The saturation currents of non-PMA devices were 104 times larger than PMA devices. Less oxide charge will induce less coupling. These mechanisms were validated through TCAD simulations. Furthermore, the impact of oxide charges on photo-sensing was discussed, revealing that oxide charges enhanced the light absorption area and increased photon-induced carriers. However, the PMA devices showed a larger light-to-dark current ratio (>300) due to a smaller dark current.

Shared mooring system designs and cost estimates for wave energy arrays

For floating renewable energy devices to become more cost-efficient and commercially scalable, their mooring system designs must be low-cost and suited for large-scale installations. Large arrays of floating devices, such as wave energy converters (WECs), will likely be designed with an individual mooring system for each device in the array. However, new mooring technology advancements provide options to use shared mooring lines to connect adjacent devices to one another, reducing the total number of anchors in the array, thereby reducing material use and cost. This paper explores the design, modeling, and cost analysis of shared mooring systems for various sizes of arrays consisting of heaving oscillating water column (OWC) WECs. Shared mooring systems for WEC arrays sized in 2×N and N×N grid layouts are designed to meet the relevant design standards, checking their performance with a nonlinear time-domain dynamic simulation, and the costs of each are calculated and compared. Several assumptions are taken in the design process to produce efficient results, providing a preliminary optimization for guidance on design decisions rather than a full, detailed design analysis. Mooring system costs per WEC were found to decrease as the number of WECs in the array increase, up to certain array sizes. The 2 × 3 array had the lowest mooring system cost per WEC out of all arrays considered, with a 60% cost reduction relative to using individual mooring systems. The 3 × 3 and 4 × 4 arrays achieved a 50% cost per WEC reduction. In addition to these significant cost reductions, the shared mooring system designs can provide advantages through smaller mooring system footprints, lower installation times, and less seabed disturbance.

High heat transfer plant-inspired neural network structure controlled by variable magnetic field

Efficient heat dissipation and thermal protection present urgent challenges in high-power integrated circuits (ICs). Although applying a coating of highly thermally conductive materials on the surface of ICs is anticipated to mitigate heat concentration issues, ensuring thermal protection for adjacent devices continues to pose a challenge. Inspired by the microstructure of unidirectional nutrient transport in plant roots, this study utilizes magnetic liquid metal droplets to develop a high thermal conductivity network capable of adaptively manipulating the heat transfer path. This approach aims to tackle the challenges of heat concentration, disordered thermal dissipation, and thermal protection for high-power ICs, thereby enhancing thermal management efficiency. By controlling the distribution of the magnetic field, this study orchestrates the structure of the thermal conduction network to ensure rapid and orderly heat dissipation of ICs while simultaneously validating the network's thermal protection performance. The temperature in the IC thermal concentration zone reaches thermal equilibrium at 399.1 K when the ambient temperature is at 295 K. As the ambient temperature rises to 333 K, the temperature in the IC heat concentration zone stabilizes at approximately 400 K. Simultaneously, the temperature at a specific point in the thermal path of the network registers at 341 K, with the temperatures of the devices flanking this point at 314 K. The magnetron thermal conduction network, inspired by the root structure of bionic plants, not only boosts the thermal management efficiency of ICs but also shows promising application prospects in aerospace, electronics, and other related industries.

Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material.

Breakdown Characteristics of GaN DMISFETs Fabricated via Mg, Si and N Triple Ion Implantation.

Mg-ion-implanted layers in a GaN substrate after annealing were investigated. Implanted Mg atoms precipitated along the edges of crystal defects were observed using 3D-APT. The breakdown characteristics of a GaN double-diffused vertical MISFET (DMISFET) fabricated via triple ion implantation are presented. A DMISFET with Si-ion-implanted source regions was formed in Mg-ion-implanted p-base regions, which were isolated from adjacent devices by N-ion-implanted edge termination regions. A threshold voltage of -0.5 V was obtained at a drain voltage of 0.5 V for the fabricated vertical MISFET with an estimated Mg surface concentration of 5 × 1018 cm-3. The maximum drain current and maximum transconductance in a saturation region of Vds = 100 V were 2.8 mA/mm and 0.5 mS/mm at a gate voltage of 15 V, respectively. The breakdown voltage in the off-state was 417 V. The breakdown points were determined by the boundary regions between the N- and Mg-implanted regions. By improving heat annealing methods, ion-implanted GaN DMISFETs can be a promising candidate for future high-voltage and high-power applications.

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

With the development of nanoscale circuit technology, the on-track error rate of digital circuit and the effect of single event upset have become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop device has been carried out extensively, including 65 nm, 90 nm, and 130 nm. However, the research on 55 nm DICE latch has not been reported. Using a three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verify the reinforcement performance of the DICE circuit, and clarify the effects of different incident conditions on DICE circuits. At the same time, we carry out a comparison of anti-SEU performance between NMOS transistor and PMOS transistor in the 55 nm process through comparative simulation experiments and quantitative analysis. The result shows that one of the important factors is the LET value which affects the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of device and increase the peak of voltage. In addition, the difference in charge-sharing mechanism between transistors leads to the recovery time of PMOS higher than that of NMOS. As the angle of incidence increases, the charge-sharing mechanism between adjacent devices is enhanced, and electron-hole pairs ionized in sensitive regions increase. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE device before practical application. Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes. Simulation result shows that the distance between the MOS transistors in the 55 nm process cannot be less than 1.2 μm. The relevant simulation results can provide a theoretical basis and data for supporting the study of the physical mechanism of SEU and reinforcement technology, thereby promoting the application of memory devices to the aerospace field.

Microfluidic platform using focused ultrasound passing through hydrophobic meshes towards automatic biological experiment

Laboratory automation is critical in improving productivity and data quality. Droplet-based microfluidic systems offer a solution that enables parallel handling of small samples with high reconfigurability and scalability. The most common technique is electrowetting-on-dielectric (EWOD), which manipulates droplets by exploiting the imbalance of wetting. However, this method is often limited by biofouling. In our previous study, we proposed a novel microfluidic platform using focused ultrasound passing through a hydrophobic mesh, which reduces the contact area and thus the hydrophobic interactions and electrostatic attractions of biomolecules. Our platform demonstrates the manipulation of protein-rich droplets at concentrations up to 1 mg/ml without the need for any additives. This is a significant improvement over existing EWOD methods which are limited to handling samples with protein concentrations as low as 0.005 mg/ml without additives. Here, we further investigate the influence of protein concentration, pH, and buffers using fluorescence microscopy to determine the effect on the system. Our platform also provides basic functions such as moving, merging, and splitting, as well as superior jumping capabilities. With reduced biofouling and the ability to directly transfer droplets to adjacent devices and multi-step processes, our platform opens up new possibilities for the automation of biology.

Impact of material and tunnel barrier quality on spin transport in a CVD graphene non-local spin valve device array

Wafer-scale graphene films produced via chemical vapor deposition (CVD) are now commercially available, however these films inherently contain randomly distributed defects such as adlayers and grain boundaries. This report discusses the impact of these defects on the signal integrity of an array of graphene-based non-local spin valves (NLSVs). It was found that critical spin parameters fluctuate drastically between adjacent identical devices. Investigation of the channel quality indicated that adlayers do not affect spin signal significantly even when located directly in the spin transport region of the device. In contrast, grain boundary defects within the spin transport region have significant impact on spin signal. Poor tunnel barrier integrity due to residue from the fabrication process also remains a dominant factor driving device variability.

Nanograin network memory with reconfigurable percolation paths for synaptic interactions

The development of memory devices with functions that simultaneously process and store data is required for efficient computation. To achieve this, artificial synaptic devices have been proposed because they can construct hybrid networks with biological neurons and perform neuromorphic computation. However, irreversible aging of these electrical devices causes unavoidable performance degradation. Although several photonic approaches to controlling currents have been suggested, suppression of current levels and switching of analog conductance in a simple photonic manner remain challenging. Here, we demonstrated a nanograin network memory using reconfigurable percolation paths in a single Si nanowire with solid core/porous shell and pure solid core segments. The electrical and photonic control of current percolation paths enabled the analog and reversible adjustment of the persistent current level, exhibiting memory behavior and current suppression in this single nanowire device. In addition, the synaptic behaviors of memory and erasure were demonstrated through potentiation and habituation processes. Photonic habituation was achieved using laser illumination on the porous nanowire shell, with a linear decrease in the postsynaptic current. Furthermore, synaptic elimination was emulated using two adjacent devices interconnected on a single nanowire. Therefore, electrical and photonic reconfiguration of the conductive paths in Si nanograin networks will pave the way for next-generation nanodevice technologies.

Buckling Behavior Analysis of Thin-Walled Cylindrical Shell Structure Under Localized Axial Compression Load Based on Initial Imperfection Sensitivity

In practical engineering, a thin-walled cylindrical shell structure is more easily subjected to localized axial compression loads caused by external adjacent structures or devices. However, until now there are few studies to reveal the buckling behavior of cylindrical shells under such nonuniform loading conditions based on initial imperfection sensitivity. Therefore, buckling analysis of cylindrical shell under localized axial compression loads is investigated in this paper. Based on the buckling test, the influence of the morphology and amplitude of measured initial geometric imperfection are studied using the finite element method. Meanwhile, the inherent reason for initial geometric imperfection affecting the buckling load is elaborated. The influence of amplitude, distribution range, and different combinations of local dent imperfections are also elucidated. In addition, the effects of inclined loading imperfection and uneven shell thickness distribution imperfection are analyzed in the form of deterministic numerical simulation. Finally, a new buckling load knockdown factor that can reasonably consider the influence of loading imperfection and shell thickness variation imperfection is proposed. This work elucidates the initial imperfection sensitivity of the thin-walled cylindrical shell structures under localized axial compression load and can provide useful guidance for the buckling design and preventing buckling failure of these structures.

Impact of device-to-device interference in nanosheet field-effect transistors

Nanosheet field-effect transistors (NS FETs) are a promising candidate for extremely scaled logic devices beyond FinFETs. The benefits of NS FETs include superior design flexibility and gate controllability, which enable continuous scaling beyond the 3-nm process node, while improving power consumption and performance as well. Recently, many reports have covered how geometrical changes such as the number of stacked nanosheets, inner spacer thickness, and gate stack structures, impact the characteristics of NS FETs. However, few studies have documented the interference effects of multiple NS FETs, even though this is quite important to actual CMOS circuit operation. In this work, we investigated the impact of device-to-device interference on the electrical behavior of adjacent NS FETs using TCAD simulation. We demonstrate that both off-state current (IOFF), and short-channel effects (SCEs) immunity, are significantly affected by adjacent NS FET's on/off operation. Further, we also determined the optimum device structure for maintaining the desired IOFF and SCEs immunity, which can be implemented by adjusting key geometrical parameters, including inner spacer thickness (TSPACER), gate length (LG) and STI collapses (Tcollapse). The superb gate controllability with deeper STI collapses results in much better SCEs properties in terms of IOFF, threshold voltage (VT), and subthreshold swing (SS), providing a promising way of reducing the local variation in NS FETs induced by adjacent devices.

Thermal Analysis and Junction Temperature Estimation under Different Ambient Temperatures Considering Convection Thermal Coupling between Power Devices

The convection thermal coupling between adjacent power devices in power converters is dependent on the ambient temperature. When the ambient temperature changes, the convection thermal coupling also changes. This results in an inaccurate thermal model that causes errors in the prediction of the thermal distribution and junction temperature based on a fixed ambient temperature for power devices in converters application. To solve this variable-ambient-temperature-related issue, a thermal coupling experiment for semiconductor power devices (the MOSFET and diode) was performed to discuss the influence of the thermal coupling effect between adjacent devices and the FEM (Finite Element Method) thermal models for the power devices considering the convection thermal coupling are established. Through these simulations, the junction temperatures of devices under different ambient temperatures were obtained, and the relationships between the junction temperature and ambient temperatures were established. Moreover, the junction temperatures of power devices under different ambient temperatures were calculated and temperature distributions are analyzed in this paper. This method shows a strong significance and has potential applications for high-efficiency and high-power density converter designs.

Generation rate of quantum gravity induced entanglement with multiple massive particles

We investigate the generation rate of quantum gravity induced entanglement of masses (QGEM) in setups with multiple quantum massive particles, among which only the gravity interaction due to the Newton potential is taken into account. When the distance between any two adjacent Stern-Gerlach devices is fixed, we consider all the possible configurations of the setup with the same number of particles. In particular, we systemically analyze the case of particle number $n=4$ and find that the prism setup with a massive particle at the center is the most efficient setup for the entanglement generation. This result can be extended to a system with multiple particles up to seven, where the entanglement efficiency is also enhanced in comparison with the setup with fewer particles. This work provides the strategy to construct the quantum gravity induced entanglement of masses setup with the best generation rate of entanglement.

An approach to preventing vehicular ad-hoc networks from malicious nodes based on blockchain

This study presents a revolutionary blockchain-based security mechanism that authenticates vehicles and instantly alerts other vehicles to unlawful messages. Access should only be allowed to authenticated vehicles in order to increase the network security, and access should be restricted or revoked for any vehicles that exhibit inappropriate behaviour. Vehicles linked to the Vehicular Ad Hoc Network (VANET) can share data and take immediate action with the help of adjacent infrastructure devices, like streetlights and traffic signals, as well as with one another. In order to maintain efficiency and safety, an intelligent transportation system depends on the flow of information between vehicles. Intelligent vehicles are vulnerable to hacking attacks because they have numerous technical flaws. A proposed security scheme identifies malicious nodes and detects forged messages, based on multiple factors like sender reputation, time and distance effectiveness. This is accomplished by employing environmental sensory data and authenticating the packets, allowing a vehicle to add numerous blocks to the blockchain. Research has been conducted on the bases of safety protection for vehicle systems as a result of security concerns. When the proposed approach is tested on different vehicle and attacker densities, the results indicate that it has a lower authentication delay and higher communication overhead than the other existing approaches. This study explored various threats from malicious nodes and the techniques in which our proposed methodology handles such attacks.

Spatio‐Temporal Correlations in Memristive Crossbar Arrays due to Thermal Effects

AbstractMemristive valence change memory (VCM) cells show a strong non‐linearity in the switching kinetics which is induced by a temperature increase. In this respect, thermal crosstalk can be observed in highly integrated crossbar arrays which may impact the resistance state of adjacent devices. Additionally, due to the thermal capacitance, a VCM cell can remain thermally active after a pulse and thus influence the temperature conditions for a possible subsequent pulse. By using a finite element model of a crossbar array, it is shown that spatio‐temporal thermal correlations can occur and are capable of affecting the resistive state of adjacent cells. This new functional behavior can potentially be used for future neuromorphic computing applications.

Amorphous ITZO-Based Selector Device for Memristor Crossbar Array

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.

Direct Writing of Aligned Conjugated Polymer Micro-Ribbons for High-Performance Organic Electronics

Organic semiconductors (OSCs) and relevant devices have presented their great potential in flexible and wearable electronics. Controlled solution deposition of organic semiconductors at a limited local region is highly expected because it can realize feasible and low-cost fabrication of highly integrated devices with low current leakage and free crosstalk between adjacent devices. Here, we reported a feasible microscale meniscus-guided direct writing method to purposely deposit conjugated polymer poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2-yl)thieno[3,2-b]thiophene)] micro-ribbons at preset local regions. The direct writing of OSCs was carried out on a microscale with the width of written micro-ribbons down to 5 μm, which was seldomly reported before. Direct writing operation induced anisotropic crystallization of organic semiconducting micro-ribbons, which further enhanced the electrical performance of organic transistors with a device on/off ratio of 5.1 × 104 and carrier mobility of 1.05 cm2 V–1 s–1. Small-angle X-ray diffraction analysis further proved the existence of anisotropic crystallization behavior. This technique shed light on the feasible and convenient fabrication of future high-performance organic electronics.

Flexible Electronics Based on Organic Semiconductors: from Patterned Assembly to Integrated Applications.

Organic flexible electronic devices are at the forefront of the electronics as they possess the potential to bring about a major lifestyle revolution owing to outstanding properties of organic semiconductors, including solution processability, lightweight and flexibility. For the integration of organic flexible electronics, the precise patterning and ordered assembly of organic semiconductors have attracted wide attention and gained rapid developments, which not only reduces the charge crosstalk between adjacent devices, but also enhances device uniformity and reproducibility. This review focuses on recent advances in the design, patterned assembly of organic semiconductors, and flexible electronic devices, especially for flexible organic field-effect transistors (FOFETs) and their multifunctional applications. First, typical organic semiconductor materials and material design methods are introduced. Based on these organic materials with not only superior mechanical properties but also high carrier mobility, patterned assembly strategies on flexible substrates, including one-step and two-step approaches are discussed. Advanced applications of flexible electronic devices based on organic semiconductor patterns are then highlighted. Finally, future challenges and possible directions in the field to motivate the development of the next generation of flexible electronics are proposed.

Unidirectional emission of GaN-on-Si microring laser and its on-chip integration

Abstract GaN-based microring lasers grown on Si are promising candidates for compact and efficient light sources in Si-based optoelectronic integration and optical interconnect due to their small footprints, low mode volume, low power consumption, and high modulation rate. However, the high symmetry of circular microcavity leads to isotropic emission, which not only reduces the light collection efficiency, but also affects other adjacent devices during data transmission. In this study, the unidirectional lasing emission of room-temperature current-injected GaN-based microring laser was realized by coating metal Ag on the microring sidewall and integrating a direct coupled waveguide. The light was efficaciously confined in the cavity and only emitted from the waveguide, which avoided optical signal crosstalk with other adjacent devices. Furthermore, we integrated a microdisk at the other end of the waveguide as a photodetector, which could effectively detect the output power of the microring laser from the direct coupled waveguide. Therefore, a preliminary on-chip integration of GaN-based microring laser, waveguide and photodetector on Si substrate was successfully demonstrated for the first time, opening up a new way for on-chip integration and optical interconnect on a GaN-on-Si platform.

Monolithically integrated UVC AlGaN-based multiple quantum wells structure and photonic chips for solar-blind communications

High quality AlGaN material growth and chip fabrication of monolithically integrated solar blind light-emitting diodes (LEDs), waveguides and photodetectors (PDs) on an AlGaN multi-quantum wells (MQWs) wafer are presented. The strong light constraint of waveguides is confirmed, in virtue of predominant ultraviolet transverse magnetic (TM) modes in transverse transmission. Unaffected by the ambient lighting, the PDs demonstrate sufficient photosensitivity to the optical signal traveling along waveguides owing to the emission-responsion spectral overlap. When the LEDs are operated at 20 mA current, the photo-to-dark current ratio (PDCR) in the PDs is up to seven orders of magnitude, which is higher than previously reported values for self-driven nitride PDs. The responsivity, specific detectivity and external quantum efficiency (EQE) of self-driven PDs are 186 A/W, 2.54 × 1014 Jones and 8.4 × 104%, respectively. Benefiting from the effective optical isolation, the light crosstalk between adjacent devices is effectively reduced about 70%. The self-driven PDs exhibit 127/131 ns (rise/decay) rapid response in the on-chip communication. This work opens a pathway to drastically improve the ultraviolet-C (UVC) monolithically integrated systems and extends the fields of application in solar-blind communication.