Address Mapping Research Articles

A Survey of Microprocessor Architectures for Memory Management

This article presents an overview of current 16- and 32-bit microprocessor architectures that support memory management. The authors define the basic requirements for a processor to support memory management and introduce hierarchically organized memory. They describe several address translation schemes, such as paging, segmentation, and combined paging/segmentation and discuss their implementation in current microprocessors. They give special emphasis to the application of associative cache memory, and analyze and compare single-level and multi-level address mapping schemes. Futhermore, the article discusses the capabilities of current microprocessors to support virtual memory, which includes abilities to recognize an address fault, to abort the execution of the current instruction and save necessary information, and to restore the saved state and resume normal processing. The authors evaluate two methods to restart the interrupted instruction, instruction restart and instruction continuation, and discuss their implementation in current microprocessors. They also discuss protection and security issues, and evaluate two protection schemes, hierarchical and nonhierarchical.

The Belgian ISDN plans in a European perspective

The interworking of two important protocol worlds within the mail area is an urgent requirement. These two protocol worlds are on the one hand the X.400 protocols used within RARE and on the other hand the RFC822 protocol which is used in a number of mail networks like CSNET, ARPANET, UUCP. Besides the mapping of service and protocol elements the mapping of addresses is the most complex problem. At the moment two different proposals for the handling of addresses are discussed within RARE. One is the RFC987 specification and the other one is the X.400/RFC822 mapping developed by DFN responsibles. Both proposals with their advantages and disadvantages are described and a recommendation is given how both could be merged together.

Performance of the VAX-11/780 translation buffer

A virtual-address translation buffer (TB) is a hardware cache of recently used virtual-to-physical address mappings. The authors present the results of a set of measurements and simulations of translation buffer performance in the VAX-11/780. Two different hardware monitors were attached to VAX-11/780 computers, and translation buffer behavior was measured. Measurements were made under normal time-sharing use and while running reproducible synthetic time-sharing work loads. Reported measurements include the miss ratios of data and instruction references, the rate of TB invalidations due to context switches, and the amount of time taken to service TB misses. Additional hardware measurements were made with half the TB disabled. Trace-driven simulations of several programs were also run; the traces captured system activity as well as user-mode execution. Several variants of the 11/780 TB structure were simulated.

Architectural approach to alternate low-level primitive structures (ALPS) for acoustic signal processing

The input/output relationship describing a given signal-processing application in its entirety can be partitioned into a set of primitive operations which may be represented using signal-processing graph notation (SPGN) as a network of interconnected processes. A set of alternate low-level primitive structures (ALPS) can be defined to implement the operations underpinning each node in this network. This SPGN/ALPS processor network is queue driven and message based, each queue consisting of a message header and an array of data. Current systems developments have demonstrated that a small, finite set of low-level primitives is sufficient for the synthesis of the majority of acoustic-processing problems, and the paper outlines the design approach for some of these. In particular, a prime-radix DFT algorithm, FIR and IIR filter structures using constrained filter coefficients and a general purpose array address mapping element are described. In addition, system architectures based on these SPGN/ALPS networks are developed.

Contiguous segmentation with limited compacting

This paper concerns the problem of implementation of a multi-segment virtual memory with the number of segments variable in time on a memory consisting of one fixed size segment. The segments can differ in size but the size of each segment is invariable in time. For such a memory the following operations are defined: _ creating a segment of a given size, ~ removing an indicated segment, _ address mapping, i.e., calculating a physical address of a memory cell from its virtual address (a virtual address is a pair: segment address and a local address within the segment). Two groups of implementation methods for such a memory are known [ 1,3,5]: _ contiguous segmentation, paged segmentation. The contiguous segmentation is characterised by a simple address mapping operation but its segment creation requires compacting of busy segments in order to create one big free segment out of several smaller free segments. This may lead to a long segment creation time unacceptable for real time systems. E.g., for a total size of compacted segments equal to 50000 and moving (read and

A memory-management unit for the optimal exploitation of a small address space

We make a distinction between virtual memory and address mapping. Virtual memory is concerned with the mapping of a potentially large address space to a small (primary) memory. Address mapping (sometimes called memory management) is concerned with the mapping of a relatively small logical address space (e.g., limited to a 16 bit address) to a potentially large memory (e.g., using a 24 bit address). Memory management is in most cases used to locate the data (and the code) of several independent processes in a single large memory. This enables switching between these processes by simply switching the address map, thus circumventing slow backing store transfers. With the advent of low cost MOS-memory devices, address mapping is a simple construct to exploit mass stores without having to upgrade the basic architecture of a processor, in which the size of the logical address space is a basic design decision.

Improvements for dedicated microcomputer based systems

Efficient table processing is essential for dedicated real-time microcomputer based systems. Both hardware and software may be tailored to enhance programming and processing efficiency. A higher level assembly language (SMAL) is presented as a software tool, and address mapping is presented as a hardware tool for efficiency improvement. Use of these tools is described to implement a microcomputer based PABX. The approach saved programming time, memory space, and improved execution throughput.

On Speech Encryption Using Waveform Scrambling

This paper presents a study of speech scramblers based on permutations of samples within an N-block. It has been found that a new family of “uniform” (U) permutations (defined by the address mapping i → ki modulo N; k prime to N) is as effective as pseudorandom (pr) permutations in destroying speech intelligibility. Analytical results show the relation between input and scrambled-signal spectra, while computer simulations compare the effects of scrambling on pam samples and on codes based on adm, apcm, and adpcm. Scrambling is increasingly effective in that order, and encoding delays in adpcm can be as low as 1 to 2 ms. Finally, scrambling has been compared with frequency inversion, which corresponds to sign-inversion in every other Nyquist-rate waveform sample.

Program behavior and the page-fault-frequency replacement algorithm

Virtual memory is one of the major concepts that has evolved in computer architecture over the last decade. It has had a great impact on the design of new computer systems since it was first introduced by the designers of the Atlas computer in 1962. A virtual memory is usually divided into blocks of contiguous locations to allow an efficient mapping of the logical addresses into the physical address space. In this paper, we are concerned with paging systems, that is, systems for which the blocks of contiguous locations are of equal size. The memory system consists of two levels: main memory and auxiliary memory. The occurrence of a reference to a page that is currently not in main memory is called a page fault. A page fault results in the interruption of the program and the transfer of the referenced page from auxiliary to main memory.

A Survey of Indexing Techniques for Sparse Matrices

Indexing schemes of main interest are the bit map, address map, row-column, and the threaded list Major variations of the indexing techniques above mentioned are noted, as well as the particular indexing scheme inherent in diagonal or band matrices. The concluding section of the paper compares the types of methods, discusses their suitabihty for different types of processing, and makes suggestions eoneernlng the adaptability and flexibility of the maj or exmting methods of indexing algorithms for application to user problems